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Executives

Franki D’Hoore – IR

Analysts

Gareth Jenkins – UBS

ASML Holding NV (ASML) 2013 UBS Technology Conference March 12, 2013 4:30 AM ET

Welcome everyone to the UBS Tech Conference. I am Gareth Jenkins the hardware analyst here at UBS in Europe. And without further ado, it’s my great pleasure to introduce Franki from ASML who many of you will know and recognize and we’ll look forward to your presentation, Franki. Thank you.

Franki D’Hoore

Thank you, Gareth. Good morning ladies and gentlemen. Lot of interference. So here we start. And the forward-looking statements we have a bit of our longer text due to some acquisition and other some things we are doing these days. The strategy is forever the same. We are in fact; we claim to be the Moore’s Law Company. So if you are interested in Moore’s Law and the progress of it, you may as well have a look at us.

Then, we are in a constant improvement on imaging overlay and productivity on existing tools, but when we look at EUV you are going to see that also in terms of EUV we have a roadmap that is pretty firm in those terms.

And then of course also looking at operational flexibility and R&D and manufacturing all the time, but this is not new, it’s just a confirmation of what we are doing for the last twenty five years.

I can’t say in the twenty five years, but certainly in several years to come, we will be further improving the immersion product line, the EUV product line and also there will be a 450 millimeter platform in the not too distant future. So, currently and this is the case for a while.

We have an immersion track and a EUV track where we are working on, where throughput and the CD uniformity have improved and where also a 450 millimeter platform is introduced. We also have the EUV track, where we are making significant process recently and it is already 450 millimeter capable, the architecture is 450 millimeter capable whereas here in the NXT platform we have to build a new platform to make it 450 capable.

Talking about all the detailed progress that we are making in immersion, it is and this is probably a bit small to read, but if you look at all the lithographic and productivity characteristics that you have to improve, it all goes in terms of overlay from 5.5 down to 5.3 and in terms of matched-machine overlay, down to 4 et cetera, et cetera and in terms of productivity over 250 wafers per hour in terms of throughput.

We have, in the last year; we have made significant efforts and also achieved significant results in making the overlay of the ASML Scanner is that, it is here, it is linked to a wafer track. In this case it’s a thorough wafer track and in the wafer track is built in a metrology tool that we call Yieldstar and its working.

All the machines are going to produce 20-nanometer technology this year are all equipped in this configuration, because otherwise, you cannot meet and achieve the overlay accuracies that are needed for double-patterning.

I have a little video animation here that shows exactly how it works. So here you have our scanner, there a wafer box came in, this is the wafer track we are going to see it from a top view now. It will move a wafer in and here it is coated with photo resist. It is moved to our metrology stage where it is measured.

It is then exposed, after exposure it goes on the development track where the photo resist is developed here and developed resist in a metrology tool called Yieldstar, it is our tool. And after the measurement, the results are put through a simulator, the simulator is adjusting all machines, it’s calculating the adjusted machine parameters that are needed for our machine and then that is correcting the machine as it all goes wafer-by-wafer.

This is really essential in terms, because if you have this machine on its own, it does overlay accuracy 5-nanometers to 6-nanometers. 5-nanometers to 6-nanometers is not good enough for double-patterning, you need to have something closer to 2-nanometers to have a double-patterning accuracy that allows yields to be acceptable and yields are related to prices wafer prices et cetera, et cetera.

So in fact, this is the key, having this is the key to be able to do 20-nanometer processing in production at acceptable cost and we have one major customer who is engaging in this and we are starting this later this year. This was immersion, but immersion, water immersion and double-patterning immersion going to be with us for a long time, you could almost say forever.

Next to that, EUV is going to be introduced. In fact, we have recently achieved quite good results in terms of feature size that’s not new 13-nanometers, 13-nanometers, but in terms of the power of the source and a stable source, we have achieved 40 watts for long, long hours in fact, what you could run in production. So this is pretty new.

And it is under the new configuration where you do a pre-pulse and then the main pulse, such that the conversion efficiency on the drop that that you have to – all the time is very reliable. Then, shortly after that, we also got results at 55, so the progress that we are making on the source these days and that’s in fact the only progress that still needs to be made because the overlay and the imaging is already gorgeous on EUV, but in terms of productivity, it’s making real good progress these days.

It is of course also related to what Cymer and us do together and we probably do it much better together today than we did in the last year and this of course all within the perspective also of us getting together as companies. We are planning to ship 11 systems this year and they are all on the floor. You could come and visit the factory, you can all see them.

Some of them are nearly finished, obviously because they ship in the second quarter. We build the new clean rooms that are all there in the EUV factory. Several of those tools though will not ship with the final source as of Veldhoven, some of them will ship with the source that is directly shipped from San Diego and that is to gain a bit of time.

But that may also be the reason why some of these machines may not all of them be revenue recognized this year and it has purely to do with the fact that the source will ship directly from San Diego and then integrated on the customer’s floor and it is only when you have light on the wafer that then you can accept for revenue recognition.

Here we have a EUV roadmap and the roadmap is not new, but we have not shown them a lot yet. But more and more we are quite confident. We were already quite confident on the imaging side of the roadmap which you see here, it’s NA of the lens and in terms of the overlay performance, and we are also quite comfortable.

The productivity what is called throughput here, the productivity you can see has a roadmap that goes in terms of power, it goes, so we have the 105 watt that is going to do the 70 wafers per hour next year. So that’s the target for next year. We have after that, a 250 watts source power which is going to be the 125 wafers per hour, that’s in 2015.

And then, we have the second generation EUV sources, we’ll have a 500 watt power and that has a throughput productivity target of 165 wafers per hour. All the rest goes hand-in-hand with the feature size and the overlay. We have certain alternatives in terms of a higher NA and a double-patterning and EUV.

So there is still alternatives on how you go to smaller feature sizes, it will all be dictated by the economics. We are very serious about EUV for anyone who would still have doubts on that. And I will not hesitate to say that it remains difficult.

As you know, we are talking and initiated last year also a customer co-investment program. The EUV money in this customer co-investment program is mainly aimed at getting the second generation of EUV on time; it’s not the first generation. The first generation is coming. It’s at our doorstep.

Just as a reminder, the customer co-investments are standing over a period of five years, a €1.4 billion combined. The run rate, so the gross will be €750 million to €800 million this year and 900 next year, this is gross, what ASML is spending there is €600 million. The additional amount is what the customer co-investors are spending.

So if you do three times, four times €300 million which is the additional 300 that they are spending in the next four years that brings you to 1.2 million and if you add €200 million this year over the 600 that brings it to €1.4 billion. So that’s how it works.

On a cash basis, it will be 100% offset, on a P&L basis, because Intel, Nexus Samsung and even TSMC, Intel is a significant related party, then in the P&L wise we cannot account for that on the R&D line, we have to account for that as they are the significant related party in the margin and in the sales. So that will have a bit of a delayed effect but it will ultimately all be compensated.

As already said, it will contribute to the EUV mainly second generation being on-time and it will also for 40% of that amount or 60% of that amount is spent on EUV, 40% of that amount is spent on 450. 450 to be introduced in 2015 and initially we started with our pilot line machines at small amounts and more and more we learn that is not going to be a small number. It’s more than two digits.

Then next to the co-investment program, we announced later in October, that Cymer and ASML are going to become one company. We are making progress on the regulatory approvals in the sense that even late last week; also Taiwan is now on the side of already approved. We still have to go for US, Japan and Korea and we continue to guide that we think that that transaction can close in the first half of this year as we have said initially.

And with this, I would like to hand over to you for questions.

Question-and-Answer-Session

Unidentified Participant

Can you still (inaudible) what was this and which sectors you think (inaudible)

Franki D’Hoore

The timing of 450 has always been for everybody, 2017, 2018, 2019-ish. In fact, 450 is a new platform. It requires new fabs and it should not surprise anyone that in fact only the real big companies are talking about 450 and not the tier-2s. So, talking about sectors is, it is in fact, you cannot really talk about what sectors are going do it, it’s mainly the three names that our customers co-investors who are talking about 450 and who plan to introduce it initially and clearly it is Intel who is taking the whole portion of 450 who is doing it first.

And that timeframe if they talk about a fine fab in 2015, 2016 and then it looks like everybody is going to initiate it in 2017, 2018. And these are our factories where it’s going to be a product mix of EUV, immersion and dry tools. So which is the whole suite of machines that you need as you need any regular 300 millimeter factories, you will need the same kind of mix in 450 millimeter apertures.

Unidentified Participant

Just as a follow-up, it sounds like most of the physics, the EUV is done you mentioned it’s just the power, are there any other issues with mass metrology chemicals or anything else which is maybe a kind of stumbling blip potential?

Franki D’Hoore

They used to be – there was still work needed to be done on those aspects, say two years ago, it looks like the progress that has been made there is of the nature where customers are telling us needed to work we were doing it, it’s considered more and more as an ownership.

Unidentified Participant

With the double-patterning, multiple patterning, does it suggest that customers will need to order more machines in the near term?

Franki D’Hoore

We have been quite publicly and if you look at the presentations that we have done in the past, I don’t have it with me now, lot of old slides I have it in it neither, but to do double-patterning, 20-nanometer, 22-nanometer for example versus the 28-nanometer node, you need on average, 1.7 times the number of immersion tools in 20-nanometer versus what you needed in 28-nanometer.

So the answer is yes, you need significantly more immersion tools to do double-patterning than you needed in single-patterning.

Unidentified Participant

And then with the metrology that’s where – that was making significant more expensive?

Franki D’Hoore

Correct. It’s good news and bad news at the same time, because they are more expensive means that it is a bit of an odd node in the total Moore’s Law, cost reduction line it’s a challenge to get the prices right. The price within the chain, because the price is for ASML.

Yes thank you very much, very nice, and that’s in fact why we have such a major effort in getting all the overlays and probably divide it right, because if you would look back 15 months, then the people up in the chain, the customers and the customer of customers who is saying we are not so sure that the wafer cost is going to be attractive enough to make plenty of designs in 20-nanometer, but we think they got that formula right.

Unidentified Participant

And is anything (inaudible)

Franki D’Hoore

No one, in fact, what should be done of note, because if you look at what people usually do with the node as well is that they form their designs and they shrink it to smaller chips within their nodes. Though the cost proportion in 20-nanometer is not attractive enough to shrink our cost, but it is attractive enough to shrink for functionality. So if you are building new devices, you are designing new devices for less power and mobility or for 4G and mobility that are significantly more a functionality then the process is attractive enough.

Unidentified Participant

Is it possible to have an update on where we are on the second question that you asked and do you have perfect visibility on what you need to do in order to get the approval?

Franki D’Hoore

I think, I do not want to go into too much detail and I think I am comfortable to reiterating the fact that we think we will close in the first half. And in fact, we are cautious with and this is why when we announced it initially, we said we think we will close in the first half and then some people said why are you so conservative, why could it not be in the first quarter, et cetera, et cetera. Now we have done this a few times before and we think it all goes rather well and we think first half is quite doable.

Unidentified Participant

I just have two quick questions. One on your major customers, Intel and TSMC has both from their quarterly reports were talking very clearly about the demand that they were going to be having for additional lithography, but then, Samsung has been kind of the one that’s been a bit less clear, have you had anymore visibility on what the orders might look like for Samsung in particular?

Has there been anymore commentary that’s been out there from Samsung about their demand? And then the other question I had is just on metrology, it seems to be a fairly recent part of emphasis for ASML, so I guess when you look at the ASPs with the various machines, when did metrology become more integrated? And how much when we think about in terms of the ASPs for the machines within 2013?

Franki D’Hoore

On your first question, the situation has not changed a lot. So, it’s still the case that the level of business that we see from Samsung could still improve significantly depending on what they are trying to do and that’s where that they are currently considering internally and we will see that they are probably in a while, whether or not it’s increasing ASML. We still believe that the guidance we gave for the business that was in the first half and then what we see happened in the second half due to the introduction of mainly 20-nanometer in logic will improve in the second half that it is quite in-depth.

Then on your metrology question, we have many, many people ignore it and actually it only became quite essential to talk about it in terms of double-patterning affordability. With the on board metrology that ASML tools have are there from day one. So, you would – I think I am not exaggerating, if you would go 20 years back and you would as a customer on the accuracy of one of our tools from a metrology point of view versus a metrology tool that a metrology maker is surveying, they would say that our tool is more accurate.

So the on-board metrology that we have for – I can say forever is very, very strong. And with an enormous amount of content on-board already. What we have done in the last three years is we saw the monster of double and multiple-patterning coming and if you look back two or four years, the likelihood that EUV was going to make it in the minds of customers.

Today in the minds of customers they think it’s close to 100%, but four years ago it was not, so you have to prepare yourself in terms of the immersion multi-patterning alternative versus EUV and that’s what we have done. And with the Brion acquisition with simulator, the simulator that is in fact at the time was aimed at making the masks ready for manufacturing design for manufacturing.

What the Brion simulator in addition has brought us is that you can simulate the whole optical column in an integral way such that you can optimize and the mask but you cannot only optimize a mask, you can also adjust machine parameters on the go for optimum printing, because you are – had a bit of drift. And it’s the combination of very fast and good simulator in combination with a high metrology tool that measures after exposure that is providing a close look.

So, from where we are sitting, it is only a bit of an expansion of what we were already doing and solving the issue of double-patterning that needs a almost immediate machine adjustment. It is true that unless that is software, it’s of course a lot of knowledge that is inside, not anyone can do this. But from a hardware and software perspective number one, the margins are quite attractive and indeed, if you load the machine fully with all options, that you could think about in terms of holistic options then the machine becomes 10 million more expensive euros.

Unidentified Participant

Thank you, just on – with Yieldstar, will every immersion tool that was shipping for 20-nanometer and whether that 20-nanometer or things that, will that have Yieldstar and is it an option to the customer or actually does it just automatically come in just being higher ASP?

Franki D’Hoore

It is an option, but it is an option that if you don’t take the option, it becomes almost impossible to make the process work at the price needed. In fact, what it all boils down to today is that, it’s that configuration that makes 20-nanometer work at an acceptable price.

What we usually do after a period of learning then we normally configure the next immersion machine as a standard machine with more options relative to what the customer is really taking all the time. So for the time being it’s an option, but if everybody takes the whole suite of options, then you may as well standardize those things. So today it’s sold as options, in the future it maybe included in the ASP of machines.

Unidentified Participant

I understand some options for flash a few years down the track once we get another shrink or two down the track, can you talk about what are the options for non-volatile memory down the road and how that’s actually thought to be?

Franki D’Hoore

Options in terms of process architecture?

Unidentified Participant

Yes, on a couple of different times…

It will be treated as a low or beyond that.

Franki D’Hoore

Well, you have three different cell and you have the 2D versus 3D structures, and that’s probably would you (inaudible). So thank you, Gareth, because there is a need for more aspects to it. Because currently, we understand that more than one customer are start to launch there the 3 bits per cell. So the 3 bits per cell versus 2 bits per cell is extending the existing capacity, because if you master 3 bits per cell, you increase instantly almost the available capacity to produce 50% more than what you could do yesterday.

So that is one aspect of what is going on today, and then going forward then it will probably already be there as of next year but certainly 2015, for people who are not too much aware of it. Currently, you have a floating gate it’s called the floating gate architecture for non-volatile memory and that means that you are injecting electrons into a gate and the issue is that the gate is becoming so small because the feature size at the number of electrons is becoming so small that you can no longer very well distinguish between a zero and a one.

So they have to make an architectural change, the life of current long over that memory is not forever and that’s where your question kicks in, because you kind of all these it’s called a bits architecture and that’s a 3D architecture. So there they build a huge number of layers in addition – in the vertical dimension and another architectural solution is a 2D solution and that one that is extendable for probably the whole length of Moore’s Law.

And that is called ReRam, resistant ram. Today it is not – very clearly the resistant ram is the promise that everybody wants and definitely intends to be there for the longer run. But in the mean time, because the technology to make resistant ram work is rather difficult.

They may have to do one or two nodes in 3D Beck’s architecture. The journey is out it’s not decided yet, that all hate Beck’s because it doesn’t have a life, it’s also awfully complicated. For lithography, if you look at the Beck’s architecture it requires, say 100 layers and not 33.

But the 100 layers are less complex in nature so it means that they can do longer with former generation sheets. If it would go to ReRam still rapidly quickly, then it would need the more complex machines and less of them but if you add it up and you make a top line simulation of all kinds of scenarios that are possible there, it doesn’t make a real difference for us. It’s complicated. It depends on customer-by-customer, you cannot draw a clear line the jury is out, decisions are not made, not for everybody.

Unidentified Participant

It could be within a year or two years?

Franki D’Hoore

It could be next year, but it could also be the one larger than the other one that we will do it. It could be the one – Beck’s and another non-volatile memory maker does something else that could also be.

Unidentified Participant

(Inaudible)

Franki D’Hoore

It doesn’t matter. It doesn’t affect us. We can manage it either way.

Unidentified Participant

Could I just ask about EUV, you talked about it progressing well. So what does that mean in terms of the context of where we are with regards with it and then secondly, as you ramp up the wattage, will the increase in wafers also be linear with that as well in terms of wafer throughput? Thank you.

Franki D’Hoore

I am afraid that would repeat a bit myself by it’s beyond that, but, we are on our way to reach with the source 105 watts by next year which relates the 70 wafers per hour. So on the first eleven tools that are shipping this year, we do not have a productivity commitment for revenue recognition. We only have a commitment that it has to expose the wafers.

So the revenue recognition of all the tools that shipped this year are non-issue from revenue recognition point of view as long as you can expose a wafer, be simply, not related to productivity. The machines that we sold for next year have a productivity commitment of 70 wafers per hour. We are in the – pushing the wrong button here. In terms of the power of the source, we were a bit over half way now.

And if you look a year back, a year back we were at less than 10 wafers an hour. So today, with a 40 watt we are doing 25 wafers an hour. The major issues in EUV are in fact more or less gone. We don’t have one big problem left. We have hundred small problems left and they are all of an engineering nature.

So that’s why increasingly we think that with the internal roadmap we have on working on all the different aspects that have to bring us to a stable source at 105 watt that relates to the 70 wafers an hour is what we said we are going to deliver and it looks like we are on our way to do it.

So that is for the machines that are shipping next year. The machines that are shipping in 2015 should have 250 watts related to the 125 wafers per hour in 2015 and that was in fact always the ultimate goal for the first generation. To get to a higher number of wafers per hour, because you see that this relates to the 125, 125, a 500 watt source which will come a few years later will give us more than 160 wafers per hour.

Now, the current architecture of the CO2 laser it’s a metal cutter that Trumpf is making in Germany and supply with company. It’s a CO2 laser; it’s a laser that’s used in the car industry. For example, it cuts through steel. The current laser is existing. There is not a laser that is able to do 500 watt yet. So that’s a major development. So, just to put it into perspective, to get the first generation of EUV right all the elements are there. It’s a question of incremental improvements.

The next generation of EUV we are talking now three, four years down the road, five years down the road, needs as depicted he re, it needs more complex lenses and it needs a more complex laser as well. Of course everything is going to become more complex in the mean time, but it’s all, I would say that once we know how to do 70 wafers per hour and that would be next year, then it all becomes from where we are sitting it becomes really evolutionary. It’s a lot of work, but you know what you are doing.

Unidentified Participant

What’s the combination of wafer pass or is it a combination of wafer pass and 450 that gets you back on Moore’s Law where we are looking at cost reduction and productivity improvements as opposed to?

Franki D’Hoore

In fact 450 is taking you below Moore’s Law. The productivity that we show here on EUV are good enough to have it on Moore’s Law. What you see is that, if you take the decision to go early on 450 you get an additional 40% cost reduction on top of and depending on who you are and what your strategy is and what your competencies are, something they can do little bit later and something they have to do little bit earlier, but that is due to the specific situation where every individual customer is in and I will hesitate to comment on that.

Unidentified Participant

On EUV will your machines be only compatible with the Cymer light source or will it have to be compatible with other light sources?

Franki D’Hoore

It is today, as we have done forever, we define an interface and if you tomorrow can bring people together who attach a source to our machine with that interface and at a better cost you will be able to. So you are invited. Actually it’s just as a site we are currently qualifying all the machines on the floor with a former generation source that is not signed and which is individual.

Unidentified Participant

Also on EUV, you have this roadmap primarily focusing on the light source, well, the whole wafers per hour?

Franki D’Hoore

Short-term, yes, longer-term you have to focus on all the aspects across.

Unidentified Participant

Are you comfortable with the rest of the supply chain, so in terms of the developments that need to be done in photo resists, photo masks, mirrors is that something that could, you comfortable it will be delivered by the rest of the supply chain?

Franki D’Hoore

One thing you learn when you are in semiconductors is that, you are in a life where you are never comfortable. But, as I said, also related to Gareth’s question, the rest of the ecosystem is up to a level where the customers are not too worried in terms of – we are managing the suppliers now it’s fine. It’s okay.

Unidentified Participant

In terms of the EUV option, if it fills up the logic camp maybe that’s brought forward or accelerated EUV expectations, what is that? Is it for resolution purposes? Is it just that they’ve now got line of sight on the development roadmap and you’ve got what accelerated the roadmap?

Franki D’Hoore

I guess, it’s just – it’s reality. Reality related to the fact that if you look at a NAND device, a NAND device is a rare type of structure and mainly in one dimension. If you look at a DRAM device from a design perspective, it is also a RE kind of structure, it’s a matrix as well. But now the dimensions in two dimensions are involved, the criticality in two dimensions in the body.

If you look at a logic device, it is also usually called random logics and it is not an array, it’s not a matrix kind of structure. It is a very randomly laid out design very often and if you go look at what you can do in term of imaging complexity on a regular structure versus an irregular structure, you can always stretch existing techniques further on a matrix side of approach.

On the random logic layout, it’s always more difficult. Now, four years ago, when people started to look at double-patterning and space and all that – there is even different approaches you can take in how you do double-patterning. They were all excited and they all thought that they were going to bring the Moore’s Law forever.

The more you start to look into the details where an eagle is it looks like when you go to a 14-nanometer logic design, which they will call 10 or 11 or 9 in terms of nomenclature they also call 20-nanometer 16 and 14 and it’s one big mess in terms of how do you call it. But if you look at it in terms of lithography point of view, 14-nanometer lines which is the next generation. It comes after 20 is awfully, awfully difficult in double-patterning left below multiple-patterning and if at all you are able to do it, you are imposing yourself a lot of design restrictions, limitations and also at significant higher cost.

Gareth Jenkins – UBS

Very useful. That was the last question. So thank you very much.

Franki D’Hoore

Yes, I scared you in the morning and all the rest of the day will be much better.

Gareth Jenkins – UBS

Thank you.

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Source: ASML Holding Management Presents at 2013 UBS Technology Conference (Transcript)
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