High Frequency Trading Is a Zero-Sum Game: Impact on Intel, AMD

Recently, I had the opportunity to read a technical story that I completely agree with.

I asked the head of a major high-frequency trading operation if there was any reason to go with FPGA's for trading instead of PCs. His response was worth a million dollars: The bottleneck is no longer with computing capacity, but with the exchange itself.

I happen to know the architect of the Nasdaq's system, and, well, after conferring with him, my opinion is that there's no improvement to the speed of the exchange in sight. So, where does the opportunity lie for high-freq trading desks? Retail flows. Look for a consolidation in the marketplace of the high-freq traders. The flows will be ripe at the major brokerage retailers--the ones that have a high volume of small transactions. The problem is that there are only a few.

How does this impact the chipmakers? Well, as a power user (software architect) of the latest chipsets, I can tell you that the bottleneck is not really in the chips anymore. Maxing out even a laptop's CPU is actually a somewhat difficult task for me to do. The bottleneck is in what's known as the system bus. That wire that connects memory to the CPU is just too long, and the speed of light is starting to become the limiting factor. The fact that the memory chip is 3 or 5 cm apart from the CPU matters.

What does this spell out for the chipmakers? Nothing good. Between this speed of light limiting factor, and the potential loss of a market segment, the chipmakers are up against the wall. Add to that the increasing ease of custom programming FPGA's for specific tasks instead of buying the latest and most expensive 100-core chipsets, and you have several billion-dollar growth stories cut short.

Intel (INTC) has something of a buffer because they've diversified, but AMD is in trouble.

Disclosure: No positions, yet

Comments

[PeterB:]

April 1st was nearly four weeks ago. So can one seriously think to program an FPGA to do NASDAQ's trading operations faster than a CPU? Naw, there is no way this makes sense. Yes, the I/O is a bottleneck for any computing system (just watch the disk drive light when you load or save a big spreadsheet), but it is not going to get better for an FPGA. Having more memory on the CPU itself is a better way to improve performance. I have been designing ICs for 46 years, and have programmed computers and FPGAs in passing.

Apr 28 04:43 AM

[MarkitWacha:]

Unfortunately, the CPUs in the High-Freq desks tend to be dragged down by thread context switching. That's something that doesn't happen with an FPGA. I love PCs, but there's something to be said for single-purpose design architectures.

My real point of the article is that the speed of light has become a limiting factor for chip design and for communications, and that the Internet latencies would have to be virtually eliminated for the trading community to want to purchase the latest chipsets based on the concept that faster trading equals more profits. The bottleneck for this problem domain has shifted to the communication links.

May 10 11:43 AM

[MarkitWacha:]

One of the players in Chicago recently started a project where they'll re-write the PC link layer to optimize their high-freq desk. That's what I expected. In this case, they're writing their own version of IP to accomplish the goal of even lower latency. I suspect that they'll cut down the size of the IP headers, for instance, and create their own protocol.

They'll be needing I/O completion ports, or the Unix equivalent, I imagine.

I suppose that they'll be shortening the cables next to squeeze a few more nanoseconds out of it. I could recommend to them the instantaneous communications possible with quantum effects (see IBMs research), but to date that process is about 100 baud. That might work for Mars missions or interstellar missions, but not for high-freq desks.

Jul 08 04:07 PM

[Scalpulator:]

Thus infiniband my friends, but we're talking microseconds here...

Jul 13 09:14 AM

[Yianni29:]

So are these trading firms adding the logic that makes a trade decision on the FPGA itself? Are they using multiple FPGAs that are daisy chained?

In other words, are they placing an FPGA as close as possible to the exchange and then using VHDL or Verilog to program the FPGA with the latest parameters for an ultra-fast trading response?
I wonder how low their true latency numbers are. I hear all the time of firms with 100 microsecond latencies... etc, but in reality they are just talking about how fast they get the market data formatted/processed and sent to their regular intel processor

Aug 05 05:48 PM