The introduction was given in part I. Here's an excerpt:
"What is necessary now is to understand the current status and future prospects for Intel's mobile communications product developments. Towards this end, in this article I will begin reviewing the ongoing work and reported progress from Intel, in particular, a recent 2013 paper by Hasnain Lakdawala et. al.  out of Intel, Hillsboro, Oregon."
In this article, part II of the series, I will focus on the process advancements reported by Intel (INTC) in .
Prelude: What is a transistor?
The first part of Intel's work in  is all about improvements to transistor design, so let's take a second to recall some basic information about transistors. Transistors are the basic building blocks for logic circuit design, i.e., design for manipulation of digital signals. I must have read about transistors on Wikipedia 10-20 times, and had them explained to me 4-5 times, but I still wasn't sure if I knew what a transistor means. To try to break this deadlock, I dusted off my introductory engineering circuits book from undergrad, reference .
(As an aside, that circuits class was one of the most grueling classes I took during my time at Texas, partly because I was still a neophyte to basic engineering analysis and mathematics. Still, I learned a great deal from our excellent teacher, Mark Flynn.)
The transistor is first of all a circuit element, similar to a capacitor or resistor, one of the fundamental building blocks that goes into pretty much every useful circuit. A resistor, for example, could take the practical form of a little spring in a wire circuit with a battery attached, reducing the current in the wire by converting some of it into heat. By controlling the current, the engineer can then determine how much power goes into something else that's been connected -- like your finger, if you grab a hold of it.
The principal utility of the transistor element is that it can be used for building up logic circuitry, such as so-called NAND gates or NOR gates. These gates implement in hardware the Boolean operations such as AND and OR. These operations in turn can allow for construction of circuits for control protocols, such as maintaining an air condition thermostat within a specified range. These operations also form the building blocks for digital computers, which allow programmers to write code with mathematical operations like add, multiply, and divide, as well as logical operations between two or more coded variables.
Transistors make use of a relatively simple yet novel material layout and selection to perform a task somewhat similar to a diode -- a circuit element that allows current to flow one way through a circuit, but blocks it off when it tries to flow the other way. The basic composition of the transistor comes in two forms called PMOS and NMOS transistors. The type of transistor determines in which direction they act as a gate for the current. By composing a circuit with several PMOS and NMOS transistors, logic functions may be built up. For example, a simple NAND gate may use two PMOS transistors in parallel and two NMOS transistors in series.
The true beauty of the transistor is in its compactness and elegance of design. It can be implemented in a very small physical region, requiring only a few different kinds of materials. Thus, many transistors can be packed into a small region to enable large functional capabilities in an extremely compact form. Most of all, this makes building them extremely cheap, which in turn enables design iteration to proceed at a rapid pace.
The remarkable design principles of the transistor have enabled the ongoing progress of Moore's law. Furthermore, transistors perform faster and better at smaller sizes -- at least historically. The fact that transistors actually perform better as they shrink has been a miraculous engineering style example of having your cake and eating it, too.
It's perhaps fair to say that the transistor has been the sweetest discovery in the history of technology. Most hardware has no right to function this simply or effectively, and with this much room for constant improvement and optimization, via the mechanism of shrinking. One has to be deeply envious of how electrical engineers can do so much with such basic building blocks.
Base 32 nm process with triple transistor architectural design
The first section of  introduces the 32 nanometer process used for building the SoC. The process includes three types of transistors,
- high performance, in two sub-sets (HP for high performance and SP for standard performance)
- low power, useful for SoC products (LP)
- and high voltage I/O transistors (HV I/O).
The details of the RF process are given in , and the RF enhancements to the process technology were reported in . Here I assemble a list of important design specs for the SoC:
|NMOS drive current (logic transistors) ||1.12 mA/um|
|PMOS drive current (logic transistors) ||0.87 mA/um|
|I_off ||30 pA/um|
|Varactor Cmax/Cmin ||3.3|
|Varactor Q factor [1,2,3]||20|
|SRAM density (high-density) ||0.148 um^2|
|SRAM density (low voltage) ||0.171 um^2|
These design specs may seem pointless or unnecessary right now, but they will come in handy later on down the road, when we can hopefully compare them side by side with design specs released by TSMC (TSM), Samsung (OTC:SSNLF), and/or GlobalFoundries.
The NMOS/PMOS drive currents reported in  indicates that Intel has selected the relatively more efficient SP type process (versus HP process) for the logic circuitry of the SoC. The HP process was probably reserved for the higher power desktop and to a lesser extent laptop processors, codenamed at the 32 nm node as Westmere and in the Tock node, Sandy Bridge. The SP process achieves the more efficient characteristics via use of a 4 nm longer gate length and low damage implants and junction grading.
The I_off value for the low power LP process is .03% of the SP I_off and .0003% of the I_off for the high performance HP transistors. Thus these different transistor architectures have dramatically different current leakage characteristics. The current leakage characteristics of the transistor determine how much power is lost when the transistors are inactive. This is important for example in low standby and always-on circuit applications. Furthermore, this LP process on the 32 nm node is reported to be 35% faster at switching than the 45 nm process. This is an outstanding performance improvement achieved by Intel at this process shrink, a perfect example of the discussion given in the introduction above.
The triple-transistor architecture is traditionally expensive to build. Here, the implementation cost is enabled due to the SP and LP transistors sharing the same high-k gate dielectric layers . The I/O transistors use a separate thermal oxide layer underneath the high-k gate layer to tolerate higher voltages. Talk of layers should be something familiar to those who listen to ASML (ASML) conference calls and conference presentations. The amount of layers on the chip greatly determines its cost, since basically, each time you get another layer, you require another pass through a 20 million+ euro photolithography stepper. Good for ASML, not so good for Intel -- although with ASML's customer co-investment program announced in 2012, Intel practically owns something like 5-15% of ASML.
The silicon makes use of a variety of advanced structural and materials technologies to be workable, currently in the fourth generation of design. These features include:
- NMOS tensile contact strain
- compressive metal gate fill
- PMOS embedded high Ge SiGe
- and reduced proximity raised Source/Drain.
Good low Vmin and yield are reported for 291 Mbit SRAM test chips as shown below. Based on this report, I assume that SRAM yields may be characteristic of yields for the entire chip. Whole chip yield statistics do not appear to be reported by Intel here.
The SRAM operating frequency for HP vs. SP vs. LP is reported as 3.8 vs. 2.9 vs. 2.0 GHz at 1.1 V supply. These numbers show how roughly four orders of magnitude difference in leakage current provide only a factor of two increase in switching speed. Clearly, the future is lower speed -- at massively lower power.
In summary of , the triple-architecture transistor design allows for simultaneous use of high drive currents and low leakage currents in a single chip. This is perfect for SoC design, which needs its application processors -- in this case, ATOMs -- to perform at high speed, alongside of other circuitry for cameras, baseband, or whatever, which has no need to operate at the same speed or power. The use of different kinds of transistors for different functions is an important mainstay for transistor design .
Note that ARM (ARMH) has relatively little control over optimization of these features compared to Intel -- ARM must basically choose whatever TSMC hands to it. Granted, TSMC probably makes some similar sub-optimizations available, but this must require very close collaboration between ARM and TSMC. At a later date I will try to investigate the details of TSMC's process architecture and compare it to Intel's as reported here.
RF Transistor Optimization
Advances in RF SoC design are reported in detail in . These include
- RF transistor performance improvements
- RF noise isolation
- High voltage (HV) power amplifier (PA) transistors
- and RF passive element improvements for resistors, inductors/transformers, and varactors.
I have educated myself on some general characteristics of RF silicon design by way of reference .
First, to the RF performance improvements, Vandervoorn et. al. report a high cut-off frequency of 420 GHz. This frequency determines the maximum RF frequency the transistors may operate at before strong signal attenuation is incurred. Presumably, this reported cut-off frequency is much, much higher than anything that the circuit will be needed to do, since for example the WiFi frequency standards are the 2.4 GHz and 5 GHz bands. So this is like having a car with Mach 5 the maximum limit on the speedometer, when the speed limit on your roads is capped out at 60 mph -- maybe 70 if you live in Texas. Still, the 420 GHz speed is useful e.g., for purposes of comparison.
The noise characteristic of the transistor is an important figure of merit for the transistor design . Here, Intel reports on the use of several novel features for the reduction of noise, including:
- guard rings,
- deep n-well transistor design,
- and high resistivity substrate.
The latter feature in particular is a simple but important mechanism for reducing noise -- usually, the resistance of the silicon is not optimized for RF operation. By use of different materials, these characteristics may be improved. The use of a P/N/P guard ring improves noise isolation by 18 dB -- the further use of a deep n-well provides a further improvement of 35 dB. These mechanisms are drawn schematically below:
A high voltage PA transistor is reported with excellent breakdown characteristics, over 7V, compared to a standard 3.3 V breakdown I/O transistor in a prior design. This is important because CMOS PA voltages at the drain were reported as up to 5 V -- making the old I/O transistor types inoperable. This appears to have been a "make or break" type of advance.
Lastly, passive elements such as inductors with excellent quality factors (Q) are reported. The quality factor is a measure of the undesirable resistive losses due to the intrinsic inductor construction. The highest Q possible is desired, and earlier on in RF design, CMOS inductors suffered from very poor Q . Vandervoorn et. al. report a peak Q of 25 on a .5 nH inductor at 2 GHz. Other accomplishments include:
- differential varactors, with reported Cmax/Cmin = 3.3 and minimum Q of 20
- Metal finger capacitors with Q of 50-100 at 10 Ghz, with capacitance matching of .1% for 100 fF.
- and precision resistors with tightly controlled variation and matching.
Substantial progress in RF transistor design has been reported in , building on the work of  and . Intel's competitors TSMC, Samsung, and GlobalFoundries have undoubtedly looked on with substantial unease. In part III, I will review the reported advancements in SoC design.
 Lakdawala, Hasnain, et al. "A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver." (2013): 1-13.
 C. H. Jan et al., "A 32 nm SoC platform technology with 2nd generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications," in IEDM Tech. Dig., 2009, pp. 647-650.
 P. Vandervoorn et al., "A 32 nm lowpower RF CMOS SoC technology featuring high-k/metal gate," in Proc. Symp. VLSI Technology, 2010, pp. 137-138.
 Allan R. Hambley, "Electrical engineering: Principles and applications", 3rd edition, Prentice Hall, 2005, chapters 7 and 12
 Burghartz, Joachim N. "Silicon RF technology-the two generic approaches." Proc. ESSDERC. 1997.