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I take reader criticism very seriously, and there is a real desire from those more critical on my works to more deeply justify my thesis that Intel's (INTC) gross margins should not be adversely affected by participation in the tablet market. I would like to lay out the assumptions upfront so as to avoid any confusion:

  • I assume that the average selling price for an Intel PC platform to be $110 (this includes the CPU + platform controller hub)
  • I assume that the average selling price for a tablet system-on-chip to be between $20 - $40, depending on the performance/features. My expectation is that the latest "Bay Trail" parts will come in at the high end of the range at $30 - $40, while the previous generation "Clover Trail/Clover Trail+" Atoms service the <$30 range. I could even see an incremental opportunity for Intel to ship single core "Medfield" Atoms into the sub-$100 tablet market, but in the interest of simplicity I will omit this, especially as I am not aware of any real design win momentum in this space currently.

I begin the piece by discussing die sizes.

How Much Silicon Does A Haswell-ULT Have And What Does It Cost?

Here is an image of the "Haswell-ULT" part that goes into Ultrabooks:

We know that the "SoC" part of it (the one with the "4th Gen Core" label) measures in at 177mm^2 on the 22nm process. To come up with an estimate of the die size of the 32nm PCH that is present on-package, I note that the PCH is, when rotated 90 degrees, roughly the same width as the main portion of the chip. Replicating the PCH next to the main part of the chip shows that the 177mm^2 part of the chip is roughly equivalent to 2.25 PCH dies, which suggests that the die size of the PCH is 78mm^2. This means for a single Haswell for the Ultrabook, Intel is selling 255mm^2 worth of chip content (177mm^2 built on the 22nm process, 78mm^2 built on the mature 32nm process).

Now, keep this in mind and note that the average selling price for a PC processor + PCH for Intel is ~$121, as I demonstrated in my previous piece. Further note that Intel's corporate gross margin if you remove the excess capacity charges is typically in the low 60% range; let's assume 60% for simplicity. Since gross margin is defined as:

Gross Margin % = (Revenue - Cost of Goods Sold)/Revenue *100

With this definition firmly in hand, and since we know gross margin % = 60, and we know revenue is $121, we then infer that the cost to build the complete "Haswell" platform is $48.

From this, let us talk about Atom.

Atom: Taking Our Best Shot

We know that to make 177mm^2 of high performance 22nm Haswell content + 78mm^2 of 32nm content, it costs about $48. So, the first step to trying to figure out how much it costs Intel to make an Atom is to figure out what the likely die size is.

How Big Is A Tablet Chip?

We do not have die sizes for Intel's upcoming "Bay Trail," nor do we have a die size for Intel's "Clover Trail+" that is currently shipping. That being said, to get a general "feel" for how big a tablet chip generally is, let's look at Apple's (AAPL) system-on-chips, with die sizes listed here. Apple's very best A6X chip built on Samsung's (OTC:SSNLF) 32nm HKMG process measures in at a weighty 123mm^2. Let us assume that this is an upper bound for tablet processors in general (at least for the purposes of this discussion) and that Intel goes and maxes out its die-size credit card at the 22nm node. Let us assume "Bay Trail-T" is 123mm^2.

Something About Die Shapes

Take a look at the "Haswell" die:

Notice that it's a rectangle? The ratio of the width to the length is a bit over 4:1, while if you take a look at a "Bay Trail" potential die shot, we see that it's pretty much a square:

We need to keep these ratios in mind when attempting to estimate the # of dies that we can get from a circular 300mm wafer.

Estimating Dies Per Wafer

Now comes the fun part - estimating how many good dies we get per wafer. For this, I utilize this wonderful calculator from Silicon Edge. To do this, we need to find values for the following:

  • Die width (?)
  • Die height (?)
  • Horizontal spacing (default 0.08mm)
  • Vertical spacing (default 0.08mm)
  • Wafer diameter (300mm)
  • Edge clearance (5.00mm)
  • Flat/Notch Height (10mm)

For Bay Trail, we assume 123mm^2 die size and assume a 1:1 ratio of length to width, giving us length = width = 11mm.

For "Haswell," I am assuming a 4:1 ratio of length to width, so we do the following math (I show it all for transparency):

1. Length = 4*Width

2. Area = Length * Width

3. 177mm^2 = (4*Width)*(Width)

4. 177mm^2 = 4*Width^2

5. Width = 6.65mm, Length = 26.61mm

Now, plugging these values into the calculator above, we get 322 "Haswell" chips from the wafer, 491 "Bay Trail" dies from the wafer, or 53% more die! Now keep in mind that we also need to make the PCH chips to pair off with Haswell-ULT, so with a die size estimate of 78mm^2 (and let us assume it is square), we get roughly 772 dies per wafer. Now, remember the following:

  • The 32nm process is more mature than the 22nm process, so yields are probably better for the PCH than the Haswell CPU
  • The 32nm parts are not FinFET, so the 22nm wafers are 2-3% more expensive
  • The 32nm fabs are probably fully depreciated at this point

So, since the "Haswell" part is more complex, let's assume that we get fewer functional dies out of a given wafer than we would of a "Bay Trail" part, so for simplicity, let's assume 90% yield for "Haswell" and 95% yield for "Bay Trail." This means that from a single 300mm wafer, we should get about 289 "Haswell" parts and 466 "Bay Trail" parts.

The next step in this equation is to figure out how much a wafer actually costs? Well, resident semiconductor expert Russ Fischer thinks that $5,000/wafer is a good estimate (this, in his view, includes depreciation; it would be $3,000 without it) so let's use that for our discussion. This means that our cost per die for the "Haswell" parts is roughly $17.30, and the cost per die for the "Bay Trail" part is $10.73. Now, we cannot fail to include packaging & test, so let us assume that this nails us with a 50% increase in the cost per die. Our "Haswell" now costs us $26, and the "Bay Trail" costs us $16.095. Now, note, for the "Haswell" part we still need a PCH. So that's built on an n-1 generation process, meaning that we can now assume that it's essentially fully depreciated meaning our wafer cost is now $3,000. Considering that can get 772 dies per wafer (let's assume 97% yield, so 748 good die), this comes to a cost of $4.01/chip. Add in packaging and test overhead, and we get about $6.01 per chip.

Our "Haswell" package ends up costing us ~$32, and our "Bay Trail" ends ups costing about $16.10. This suggests that we're looking at ~73% gross margins on the "Haswell" part, and for the tablet part depending on what the ASPs for the high end parts end up being, 46% - 60%. Note that it would only take a little bit of wiggle room in my wafer cost estimates, expected selling price per chip, yield, adder from packaging & test, and so on to get these comfortably into a 50% - 60% range. In fact, given the gigantic operating margins from the data-center group, particularly as it leverages both "Core" and "Atom" core designs to save significantly on R&D, I wouldn't be surprised if Intel would eat ~50% gross margins on the highest end Atom chips but blended gross margins still stay near the high end of the range.

But you see the point, right? I don't have Bay Trail's die size estimate, I don't have Intel's wafer costs, and I don't have yield estimates, but with some pretty reasonable assumptions, we see that it is NOT farfetched for Intel to command >50% gross margins on the Atom chips and to be able to - in conjunction with the data-center group's huge margins as well as even the high PC chip margins - keep blended gross margins nice and up there.

Source: Intel: One Last Thing About Gross Margins (Die Size Estimates And Colorful Images Included)