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It is my belief that there is a very dangerous misconception with respect to Intel's (NASDAQ:INTC) 22 nanometer FinFET process being propagated on the internet. Normally, I would not bother responding to it, particularly as these days I find that I just don't need the headache, but as somebody who has kept his readers well informed about the Intel story, I feel that it is my responsibility to address it.

So, what is this "dangerous misconception" that I refer to? The notion that Intel's 22 nanometer process was not a "full shrink" from the prior 32 nanometer node, and that the "22 nanometer" node was largely a "focus on implementing FinFETs" without the attendant transistor size decrease. In this article, I lay out a counter-argument that I hope investors will appreciate.

Intel's 22 Nanometer Was A Full Die Shrink

The whole idea behind "Moore's Law" is economics - not chip performance. The "law" essentially states that every two years or so, IC designers would be able to put twice as many transistors in a given physical area. Of course, a corollary to this "fact" is that the cost per transistor goes down significantly in each generation thanks to these die shrinks. Now, let me be clear, the actual cost of the wafer goes up, but the area savings (which means more chips per wafer) on a per chip basis should be enough to more than offset the wafer cost increase.

Note that Moore's Law breaks down (that is, cost per transistor no longer goes down) if one does not "shrink" the transistors (which are what integrated circuits are made of). So if you're an investor in a semiconductor company and you start to hear that each process node does NOT provide a full node shrink, then the economics of what that company is doing are in serious trouble. Fortunately, the rumors that Intel's 22nm node was not a full shrink over 32nm are patently false, as I will now demonstrate.

So, the tough thing about comparing "process density" is that the size of a given IC isn't just dependent on the "process node" - the "name" (such as "22 nanometer") really just refers to the minimum feature size that you'll find, rather than the "average" feature size. Also, IC vendors often make trade-offs when designing a particular chip that may mask the "true capabilities" of a given process. However, luckily for investors, Intel's development cycle essentially involves building a design on a given process node, and then shrinking essentially that same design to a next generation node. From there, since the designs are very similar, it becomes mostly a process comparison.

To prove my point, I give two exhibits. First, here is Intel's "Sandy Bridge" die. It weighs in at 216mm^2 and sports 995 million transistors:

(click to enlarge)

Now, here's Intel's "Ivy Bridge" die, which weighs in at 160mm^2 and packs 1.3B transistors:

(click to enlarge)

So, let's do some basic math, shall we?

ChipProcess NodeDie Size# TransistorsBillion Transistors/mm^2 (i.e. DENSITY)
Sandy Bridge32nm216mm^20.995B.0046
Ivy Bridge22nm160mm^21.3B.008125

So, with the 32nm implementation of a given design, we get 0.0046 billion transistors/mm^2 and in the 22nm implementation, we get a much better 0.008125 billion transistors/mm^2. This is a density improvement of roughly 76% generation-over-generation. Not quite 2x the transistors in a givne area, but scaling is never quite perfect and certain design decisions may have kept the chip from scaling as well as it could have in theory. But you see the very real economic benefits here, right? For what is likely a 5-10% increase in wafer costs, Intel can sell a much more feature-rich enhancement of an older design, but at the same time sell less silicon. All of this for the same price that it was selling the previous chips! Nifty, eh?

But Wait, Was Intel's "32nm" Inferior To The Foundries'?

In a world in which Intel's product lines and those of the many semiconductor companies that utilize external foundries now seem to compete (particularly in the mobile battleground), process technology (from many standpoints - performance, power, density, etc.) is now something that investors really care about, particularly in trying to guess the competitive landscape several years out.

While I do not intend to make any such comparison in this article, I do realize that the above comparison is an "Intel to Intel" comparison, and that Intel's "32nm" starting point may not be comparable to, say, 32nm from the likes of Global Foundries/IBM Common Platform Alliance. Note that densities across different designs (which again may be optimized for different targets), we can get a ballpark estimate as long as we use somewhat similar designs. I wouldn't want to compare a pure GPU or an FPGA to a CPU, but I would be happy to compare a "pure" CPU to a "pure" CPU.

To that end, let me bring out my two examples: the first is Intel's "Sandy Bridge-EP" die - this is an 8 core, server oriented chip that weighs in at 416mm^2 and packs in 2.263 billion transistors. Built, of course, on Intel's 32nm process:

(click to enlarge)

In the other corner, I have AMD's (NYSE:AMD) "Vishera". This is a 4 module/8 core CPU product that has roughly the same cache-to-logic mix that the Sandy Bridge-EP does (although, again, this is not a perfect comparison):

(click to enlarge)

This bad-boy weighs in at 315mm^2 and packs in 1.2B transistors. Using basic mathematics, we get the following densities:

So, let's do some basic math, shall we?

ChipProcess NodeDie Size# TransistorsBillion Transistors/mm^2 (i.e. DENSITY)
Sandy Bridge-EPIntel 32nm HKMG416mm^22.26B.0054
VisheraCommon Platform/GloFo 32nm HKMG315mm^21.2B0.0038

The Intel chip looks a bit denser, but again - these are NOT the same designs (and the AMD one looks a lot more automated, which can often dent density in exchange for easier design), so a pure "Apples to Apples" process density comparison is not possible. We can, however, see that these designs are roughly in the same ballpark. This means that Intel's "32nm" was about on-par with the competing "32nm" process from the Common Platform Alliance at the time in real designs. This also means that if 32nm -> 22nm for Intel gave a "full shrink" worth of density improvements, then Intel's "22nm" really was a "full node move".

Source: Intel: Dispelling A Dangerous Misconception