Arthur W. Zafiropoulo – Chairman, President and Chief Executive Officer
Manish Ranjan – Vice President-Marketing Advanced Packaging/HBLED Market
Handel H. Jones – Chairman and Chief Executive Officer
Yun Wang, Senior Vice President and Chief Technologist-Laser Process
Jeff Hebb – Vice President-Laser Product Marketing
E. Jan Vardaman – President
Shri Shetty – Vice President-Marketing Inspection System
David M. Owen – Vice President and Chief Technology Officer-Inspection Systems
Ultratech, Inc. (UTEK) Tenth Annual Analyst Day Conference Call November 5, 2013 11:00 AM ET
Arthur W. Zafiropoulo
We have a new venue and it’s really a wonderful venue. I hope you enjoy the views that we have around the room and we have really a full group, which I want to thank everyone for coming. My name is Art Zafiropoulo and I run the company and I have for many years. I joined the company at the end of 1990. Then we acquired it in 1993, went public in 1993, so this is our 20th anniversary being a public company and it’s been a great 20 years and I’m sure that we’re going to have another 20 years of outstanding performance.
This morning we opened NASDAQ for the 9th time and I can tell you that the Senior Vice President had mentioned that 20 years ago, let’s say that we have increased the company size and profitability by about 1,500%. Unfortunately we’re going through a pause, which is sometimes good and sometimes bad, and as I said in this industry before that you make money going up, you make money going down. So I think now is the time to make money going up. So the downs are behind us and I think when you hear the presentations today, you’ll get a sense of that.
We have a full cast of speakers and we’ll try to be as efficient as possible and I will be the first speaker and talk about what I think the industry is doing? I’ve been in this industry in some form or other since 1964 and I started as a technologist. My background is statistics with EE and I pioneered many technology for IPVD sputtering and plasma [indiscernible] and also in the development of the first reduction stepper in the 1970. So I’ve been involved in this industry a very long time and I think that I transitioned from a technology person to a business person in the 70s, ran companies, fixed companies and then took this company over in the end of 1990 in September and it was discontinued by a Fortune 500 company, and we fixed it in one year after losing a considerable amount of money prior to that; and then they couldn’t sell it and we bought it, took it public. So it’s been a great story and I should share with you that when we bought this company in 1993, I gave 25% of the equity of company back to all the employees for free, actually $0.05 a share of stock.
So the employees helped the company be successful not just being solely a great team of people, many of my associates are here today. So I want you to speak with them, but don’t ask them any inside information. They have been instructed they will self-destruct if that occurs. So this is a list of some of the speakers and this is very much of what we do every year, so that we have some consistency in the speakers and you’ll hear what we all believe is going to happen both in technology and in products.
So I think the first thing that I’m going to talk about is what are the things going on and I’ll use references of public information. I don’t make up this stuff usually myself, but I this is important to see that the trends are generally up or down. However, the most important trend here is a trend for next year. This is the second year that the equipment spending and capital spending has been down and so typical cycles run two years up and two years down, but here you’ll see that the industry in 2013 has been down and wafer front-end has been down 9.1%. Last year, it was double-digit.
Next year projections are to be up 15%. I think that the trends are typically down, but I think that even if this number is inaccurate, I think what is accurate is it will be up here next year. So this should be a very good investment period for many of you. This is something interesting. This I did for a purpose is that it wasn’t that many years ago that we recognized the Japanese as really doing great inputs to the industry in semi-conductors and back in 1990, you can see the population of Japanese companies in the semi-conductor industry, it was significant, and if we move fast forward here today, in the first half of 2013, there is only one left and that’s the company primarily in memory. They were a logic manufacturer, they’re primarily a NAND Flash manufacturer and so we have Toshiba here, which is a very good company, that survived these 20 years, which is interesting how things change and we don’t recognize that and this is just like technology.
Technology changes just like this and what’s also interesting here is for the first time, we see two companies now, again 20% are fabless; Broadcom and Qualcomm; and Qualcomm today is at least close to or above Intel in market share. So here we have a fabless company versus a very powerful PC company and yet this company, Qualcomm, is a significant power in the mobile space today, but this just gives you a feel for what’s happening and the top companies really with Intel, the exception in PC base, is primarily mobile driven.
So looking at this slide, talking about the future, really this is important to talk about what kind of companies play in these spaces and here we have the premium phone and this second bullet is I think really, really important, by 2017, this will represent more than 50% of the devices made. That is a significant number and it’s not going to go away, so the premium phones or smart phones are going to be significant in the future. Tablets are very important, but as we can see here, the tablets are not anywhere near the size of the market for mobile smart phones, and so companies like Apple and Samsung will be very powerful in the future and they’ll continue to dominate the space in the markets today.
So we look at the fabless companies and market share by headquarter location. Now this is 2012, but it hasn’t changed very much. U.S companies still dominate the tablet space, so we still control designs, we use foundries to make things, but the United States still is the leader. So if you want to be successful today in the equipment space, I think you got to have presence in Silicon Valley and that’s exactly where we are, Silicon Valley. And I can tell you that coming from Boston, I lived there most of my life, I thought it didn’t matter where you live. I didn’t think it mattered, because if you had a great product and great technology and great support, you’ll be successful. Tell that to DEK, to Prime; to these companies of Silicon Valley compared, competed with 128 and I can tell you it’s not true. Location is important not just for real estate for where your company is located.
The time zone changes are very important and so we are a California based company at San Jose, California, but we had a move to Singapore to be closer to our customers, and last year, we manufactured 48% of our machines in Singapore and we have almost 70% of our sales in Asia. So you’ve got to get closer to your customers to be effective. It’s just not just making money, it just being closer to how you can make money. And this talks about the top 20 companies. Again, what’s the point in this is the importance of the back-end of packaging.
20% of these companies on this list are back-end, so packaging becomes more and more important and packaging is transitioning from front-end to more important areas in the back-end, but not putting this out of context, what that means is today at front-end with about 30,000 to 40,000 wafers starts per month, it’s about $4 billion investment. The back-end for the same equivalent production rate is about $150 million. So it’s significantly more important to be in the front-end and back-end, we’re in both locations. We’re in the back-end and we’re in the front-end. Our laser technology is in the front-end, our inspection technology is in front-end and our packaging is in the back end. So we’re a balanced company. We think both are important.
And again, you’ll see the importance here, when you see companies like ASC, you see companies like [indiscernible] and EMCORE, these companies are back-end, they are packaging companies. They’re margins aren’t great, but they buy a lot of equipment and all these companies are customers of us. Again, I want to talk about – we talked about the two-year cycles, and we can see here that two-year cycle down, two years up, two years down, so we’re going to see at least two years up, so next two years are going to be very important for investments. We think this industry – the good companies in this industry will do very, very well and there’s more than one. We are one, but there is more than us out there that are going to do very well. We think we’ll do better than the other ones, but we’ll see; time will tell.
And again looking at spending by devices, just wanted to highlight the last two years in logic has decreased and we’ve seen memory is going to be growing and primarily NAND Flash. That’s going to be a very good market and then dropping off, but again, the important thing here is the primary driver for this industry we’re in today is logic and we are today a logic centric company. I wish at times that these are more memory oriented, we will some day, but right now, we are logic centric company. So when things change in advanced technology and perhaps get pushed out because of things like FinFETs, we get punished for that, but this company is stronger than it’s ever been before.
So this is sort of a roadmap that companies would put this all public information; some thing you can believe, some thing you can’t believe, it’s up to you. But I think what’s important is that what you’re talking about is the generation of FinFETs. Now many of you know what a FinFET is, others of you maybe are not so clear about that. But the industry started in 1957 making the first transistor and the first integrated circuit in 1960, and all these circuits, these transistors and integrated circuits were plainer, they’re flat, they’re two dimensional; X and Y. So today we have 70, 80 layers in making a chip and most of them are wiring, but this is doing interconnection of the transistors, so now the transistors are flat. And what’s happening as you make the transistors smaller, you can only limit what they call the gate – the gate length is flat, so now the gate is limiting the density, Moore’s Law.
So what they do is they took this slide transistor and they moved it to vertical, they moved it to a fin as the field emitting transistor, that’s what a FinFET stands for. So now the gate can go up and back down to fin. So now we reached the gate length and that’s really important, and so that’s been limiting where this technology is going. So this FinFET technology is very, very difficult, all the modeling industry has today is with plain structures.
So they’re learning and they thought it would be less difficult and it hasn’t been, and that’s this cost we talked about in April of this year, where we announced that we thought this industry will go into pause and we also would go into a pause. We were the first ones to call it out and many analysts said is this centric to Ultratech and we said no and they looked at us, they said, gee, a small company talking about this and guess what, it’s what’s happening.
The whole logic industry is waiting for FinFETs. Well, the tunnel is getting bigger. We see the end of the tunnel. So we’re getting very close and there is one company I won’t describe today who it is, that’s in the range of 80% yield and they’ll be ramping up next year and this one factory will be around 100,000 wafer starts. It will take a couple of years to fill the whole factory up, but if they use all the processes that are qualified by our tools, if they do that, I’m not saying they are going to do it, but if they use those four steps, they’ll be $400 million worth of our equipment, just one fab, just a portion of what the industry needs.
So today, I estimate that Apple probably buys about 600,000, 700,000 wafers per year, 12 inch, I think QUALCOMM buys about 700,000, 800,000 wafers per year. Both those companies by 2017 will require more than 2 million wafers per year. So a 100,000 wafer start per year is only a fraction of what the needs are and we believe the wafer technology is an enabling technology, as is packaging to package these devices.
So moving to spending, again, we talked about the two years up and two years down. So I think the next couple of years, at least two years, and I’m thinking maybe a portion of 2017 will also grow. So I think the next downturn may occur in 2017, but I think we’re going to have two, two and a half years of a run that we also make some money. And again, looking at the growth in the equipment area again, the whole capital equipment, we see again the cycles that we spoke about before, and the reason I did that is so you read that, take it home with you and sort of look at what the history is, and what we’re talking about projections in the future.
So this chart here, you’ll see this again today, I hope you will, and this talks about each of these nodes in logic, since it’s the fastest growing area. So this node here is a 45 and 40 nanometer. So we can see here that this dropping off, and I want to remind everybody that these fabs are fully depreciated. They’re typically four or five years old, the industry runs on a five year straight line depreciation. So it’s 20% a year and I’ll share with you some of the costs of the fab and what the depreciation cost is. And then we see here, the next step here, the growth of the 28 nanometer is this growth here. And so here we’re getting to a point where all the buys recently for last couple of years had been 28. We’re beginning to flatten out, now there will be some buys there, but they will be reduced.
And then now the 20 nanometer structure is here. We see some growth here, but I want to caution everyone that this is not a major node. I want to show you some data on that, and this is a node that’s going to be the next major impact for the equipment industry and for the mobile market. Now this chart also you’ll see I hope today, and this talks about the 45 nanometer technology, it never goes away, just costs go down, it’s fully depreciated equipment and we see here still residual amount of business going on here. 32 was an interim node, so very short node, because the industry had some difficulty going to 28. So some people said let’s go 32, but now here’s a 28 nanometer node. There is a major node. There was a significant node. Industry made some major changes and this is where we had our first major entry into this market with our lasers.
And now here is a 20 nanometer node and this is where we are today. You can see it’s also a very limited node. I’d say that this node here, this 20 nanometer is about 20% to 25% of this node and that’s just what you see here, but then you see the real growth, the real growth in FinFETs. That’s the future. So those companies that participate in this node will be the winners and we are solid in this node.
This is cost per gate reduction. This is sort of a chart that talks about when do you get to the end of scaling, and cost is a factor in scaling and this is with IBS and this just shows the continued decrease in the cost per millions of gates on a ship. I put this in here to show that today we haven’t fully realized the cost savings in 28 or 20 or 14 or 16. So today, the costs are higher. They will come down, but if you know, if they’re going to come down, they are going to flatten out, there’s going to other solutions to this problem.
We talked about CapEx; this is a 28-nanometer high-k metal gate transistor. Depreciation cost is 55% of the chip cost. This is five-year straight line, again 20% a year. The equipment maintenance is getting more and more complicated, it’s 14%, consumables are 10%, direct labor is 1.4%, indirect labor is 6.56%, so you see that this equipment area is important, so you get subsidies from governments or states, people go there, people [indiscernible] here, depreciation, really, really important, so let’s take you down from 28 to 20, again, costs are going up. Let’s go to FinFET, costs are going higher.
Let’s go down now and look at those three notes, depreciation costs are going up, equipment maintenance is about flat going up slightly because the shape is getting more complicated, consumables are coming down. So I believe that people have to deal with this problem. We do, our customers do, and this is what we’re doing. We’re dealing with the real issue of cost and that’s in equipment and productivity. So we have equipment and roadmaps to increase productivity, not necessarily selling price, more wafers per machine can be very important in the success of this industry.
I want to kind of jump off just for a couple of minutes on a company we acquired last December in atomic layer deposition and why I did this. Atomic layer deposition is a very interesting technology, and is one atomic layer at a time. It’s very slow, as was PBD spluttering to 60, so I helped pioneer that 60. And so this technology is very powerful, has formal coating and it’s very good in pinholes, so a very thin-films like moisture barriers or for maybe protection, lubrication on surfaces, this technology has great promise.
And not just in semiconductors, in sensors and maybe medical sensors which I think has a great future. So, this company grew out of Gordon Lab’s at Harvard University and they had built any multiple lines, but it wasn’t a focus company. It was such a powerful technology that people tend to wonder. They don’t get focused on what a mission should be. And so when I acquired the assets in December, we moved it quite next to Brandeis University in Boston and this shows the facilities that we have there currently and we’ve maintained a full staff of PhD, so that is still there today, and we completed our move to this new facility in June.
This was really in 1978, I talked about new technology, this is what it looks like, and the ALD system that was fabricated. This almost looks like the first transistor in 1947. It’s close to I think maybe Houston that 47 here, but this is what we have today. So we’ve gone through a second generation design of the existing products they have. So this is what we call our Savannah Gen 2 and this is our PG Gen 2, it’s a larger production related system, not huge production, it’s a load lock system and we’ve redesigned the gas panels and made the system smaller and again they more capability.
So this is what we have done in the last nine months. And our projections are this year; this company was not profitable for about 14 quarters before we acquired the assets. This year, we will profitable based on the number of IC to date. And developing new programs that will focus on things that we think could be really important, important for Ultratech two, three, four years down. Not today, but in the future we are working on some technologies that will just stager you of what the potential could be. We recently did a coming out party at an AVS Conference in San Diego a few months ago, and these are the papers presented at this conference, and these were basically home-made university related hardware and this is the hardware papers that were given, and you can see Ultratech/CambridgeNanoTech had 26 papers on the systems that we manufacture. These are some of the other companies that manufacture equipment for the ALP space, but you can see what the papers had been presented for the future and this is very important, and it really truly was a coming out party. So with that, I’m going to flip it over to Dr. Jones.
Unidentified Company Representative
Good morning. I appreciate being here and I would try and tell you what we see as some of the key trends in the semiconductor industry and also the driver in the electronics industry that’s driving demand. Our projection is that 2014 will be a slightly stronger year than 2013. I think last year, we were little bit negative on 2013, because of what we saw in some cases, clearly, with demand, but mainly because of the intense price pressures in most market segments. We still see some of those price pressures, but maybe not quite as strong as last year.
The numbers that we do have now for 2013, actually a little bit higher than we originally projected because of the increase in price in memory. This has been partly because of the controlled capacity, but also because of the impact of firing of [indiscernible]. But next year, we think the demand will be relatively strong. We do see the global GDP environment being reasonably stable. So as I said, we do see fairly positive 2014. We do see right now the 28-nanometer high-k metal gates and high volume production. TSMC shift about $1.8 billion worth of 28 nanometers in Q3 of 2013. So the industry has done a tremendous job of ramping 28.
We do see 20 nanometers coming up. We do see some potential for some delays because of getting cost down. We also tend to agree with – also the 20 will not be a big technology norm. We’re tracking Intel very closely in terms of their 22 nanometer FinFET and high volume production costs are little bit high, but basically doing pretty well.
Intel has announced that they will postpone 40 nanometer FinFET’s by about one quarter. We think it will be maybe two quarters, but it’s going to happen. The industry has to go to FinFETs which I think in the Q2 to Q3 of next year you will see Intel digging high volume.
The foundry vendors again, we also see them pushing FinFET. Among what we consider to be foundry vendors we do see Samsung ahead right now or TSMC followed by Global Foundries.
The other area we are tracking is what we call 3D packaging. The conventional TSV is delayed because of high costs, but we see other forms of 3D packaging coming in quite aggressively. The initial driver is the NAND flash. Samsung has announced that V-NAND was mainly for the enterprise, but we’re pretty positive in terms of the 3D packaging, we also see 3D packaging for DRAMs. Our analysis is that the DRAM cost per bit reduction pretty much flattens out of the 16 nanometer, 18 nanometer technology nodes. So that’s going to come in next year. So I think after that technology node, I think you’ll see different approaches required for DRAM. We do see very strong growth in [indiscernible] and we are tracking mainly the logic products. That’s where we see basically a transition happening fairly rapidly in packaging.
The other area we track quite closely is the LED lighting. Again this is probably driven by China, and I’ve spent a lot of time in China because industry there obviously is growing quite rapidly. But the attempt or intent there is to replace fluorescent with LED and I think you’ll see in 2016, 2017 or latest 2018, very high volumes.
Within the industry, also you do see strong pressures to reduce power consumption. That applies obviously to the battery powered products, battery life on the 5s, maybe one day at best. Everybody would like a longer battery life, but also in terms of the servers of the server farms and of course the bandwidth requirement increases, there is actually pretty strong growth in servers’ infrastructure. One thing I also did mention, in terms of multi-chip packaging, Intel is actually using a two chip approach that has well one chip, is the processor and the other is memory.
This shows the global electronics industry. Without the global electronics industry growing, the electronics industry or the semiconductor industry would not grow because otherwise, you basically displace the value of your customers. So we do see within the global electronics industry, wireless being the key driver, and of course this includes the mobile platforms, smartphone, tablets, the connected tablets, and also the infrastructure. The wireless infrastructure will have to grow to support the growth in platforms.
This is what we show in terms of some of these activities in China. In 2012 about 82% of all the phones produced, globally were produced in China. So we do see some change in momentum in terms of demand and that in turn with change the momentum in supply in future.
So what we’ve had in the semi-conductor industry is it’s almost four years now of no growth. 2010 obviously was a boom year, but we’ve had four years of almost no growth. So from 2014 to 2020, we do see fairly steady growth maybe in the CAGR of about 7%, 8% but probably going to down year and there somewhere, we’re predicting maybe 2018, but right now that is still fairly speculated, but again we’re talking about a fairly stable environment in the next few years, that’s at the top level. At the lower level there are some significant changes happening. Again if you look at the consumption of IC products by application segments, the high growth or the strongest demand is environment. So if you look at the builder materials of the smartphones are actually going up.
Basically the processor, application processor, the application processor, prices royalty earlier on $30 and then you got the modem, so you got the transceiver, you got the PA you have the signal sensor, you have the touch screen controller. So the builder material is going up as well as the increase in volume and then of course we are also transitioning from the dumb phones to the feature phones to the smartphones. This is what we show in terms of foundry market and so we’re seeing is the foundry market taking over in increasing percentage of the total global wafer supply chains.
And again you can see this represented in this chart, where the foundry market grew from 2010 to 2013 around 44%, while the IT industry was basically flat. So what’s happening here? So two things; one is that more companies are becoming fabless; secondly, the growth of the fabless, basically the process of the fabless companies are been awarded by the cost of wafers and we think that pattern will continue. We think that maybe not – at this kind of growth rate but you see more of a value of the semiconductors being taken over by the wafers. So that can put actually some profit pressures on some of the fabless companies going forward because the other part of what is included and thus what they do is increase software content.
One thing which I think quite closely is a supply chain, again this kind of follows a bit of what we also said that today from a supply base point of view North America is pretty strong. Now this is basically the semiconductor supply base, not the wafer supply base. But you see the rest of the world basically coming up right fast and in 2020 the rest of the world will be over 30% of the total. The rest of the world includes Samsung.
So this is basically the Chinese, the Taiwanese, and Samsung and of course Samsung is a major factor in these numbers but you see now a change in the supply chain the structure of the semiconductor industry and of course this also imply some very significant things in terms of the profit pressures, the competitiveness on market share of the number of these legacy companies.
So what we’re seeing as I mentioned continued growth, the smartphone market, tablet, computer market are driving lots of technology, specific number for you is that China will manufacture about 760 million phones this year and about 150 million tablets. We are working with a company called Galaxy Core. They will produce 900 million sensors this year. And all of those are going to the China market, but 60% of the phones in China will be exported.
We are seeing intense pressures on low cost which means higher chip use and also means strong [indiscernible] use. So again this drives the migration of this one feature dimension, so when you do that so you have a high yield and of course that means management of linkage and also management of stress, I’ll be talking a bit about more of those going on later.
And as I mentioned earlier, power savings and also again part of it is it’s not only in the U.S., but also it’s starting in China because of the pollution problems. We are also seeing the content is driving the growth of infrastructure. We are very positive on the infrastructure, which will include base stations, the routers, the switches et cetera going forward.
So if you look at the amount of data that has to be processed, again it depends on where you put the point. But if you go from 2008 to 2018, it’s about a 479 multiplying growth. Now Cisco also has a similar kind of chart. And if you look inside this chart video, high-definition video is a key driver, and of course the next big phase of video is 4K.
4K will be coming in 2015, 2016. Kind of the side issue, Netflix is going to be supporting 4K video next year. But 4K video will drive huge demand for bandwidth and infrastructure. So we are kind of in a phase where one platform builds other businesses and again is the smart phone business is driving a lot of respect. So what do we see in terms of semiconductor industries that’s kind of driving or supporting the growth?
Well high performance and low power. You see multi-core devices, smaller picture dimensions and then the adoption of new technologies. The Haswell processor from Intel is an incredible choice. I mean this is a second generation FinFET. The first generation basically drove the process and pulled the process. The second one optimized the technology and of course, if you have a [indiscernible] it will be talking about nine ten hours battery life.
So we expect to see day to day similar kind of thing when you go to 2014, initial designs will be probably slightly high costs. The second generation though will then it will drive the benefit of lower power. We see better connectivity. LTE obviously is in high growth mode. This spending comes like Qualcomm, MediaTek is coming up, Intel just announced their LTE, Broadcom bought the LTE business of Renesas. So that’s a good decision or a bad decision that we’ll see. We are not convinced by the way.
We see 802.11ac is coming up very strong capability. Then also low power Bluetooth. We see low power Bluetooth driving was quite incremental things. And the initial support capability for that will be connectivity to smartphones. Things like thermostats, television, remote et cetera. So a lot of low power Bluetooth we think is going to be a major, major growth area in the next few years.
Our better sensors, bandwidth is obviously growing quite rapidly with many, many segments. Image sensors, high growth mode. If you look at the 4S the big advantage of 4S is camera capability. On that today is the Sony image sensors. But this year there will be almost 4 billion image sensors produced, that takes a lot of wafers. TSMC next year will probably allocate about 100.000 wafers a month to image sensors.
And if you look at our ARPU they’ve actually increased the size of the pixel, which increase the size of chip. Lower cost memory; DRAMs are in trouble. So now we need new architectures, we need different packaging technologies. The longer term technology though is SPP. NAND Flash were also probably in terms of scaling. So we see potentially 3D, but DRAM is probably the long-term solution. And then, we also see increased software, image recognition, video codecs, communication protocols.
So the demand is very strong. So the issue is how well the industry satisfied the demand and how rapidly will technology evolve. This we always show in terms of CapEx. This is for the wafer fabs. There seems obviously a slight decline from last year. Commitments for next year are pretty strong. Samsung probably in our opinion will be around $12 billion, TSMC, as announced, $10 billion. We think Intel with probably come in around probably around $12 billion and we see then the other companies pretty much following.
So I think next year from a CapEx point of view should be pretty strong and this is building capabilities for this impact. And of course, if one company doesn’t other companies have to follow, otherwise if they don’t they’re going to lose the chip. Other parts of the industry, 450, we see potential performance other than Intel, which is potentially Q4 2017. The probability keeps on declining. We see postponement probably up to 2020.
UV, again we see postponement, probably not likely till 7 nanometers. So what does that do to the industry? Well, it means that you have to optimize what you have, which really means reducing leakage, improving the yield, reducing stress. So spending a lot of money on the existing technology, enhancing the existing technologies. So, again, new device structure remains to be revamped for tracking on the nanography. Those are long way out. Those are long way out. So we don’t do see any real breakthrough other than potential revamp in the near-term.
And then the FinFET challenges, industry has to go to FinFET, but it’s tough. This will be very, very tough. So there’s going to have to be a lot of money spent on reducing leakage, reducing stress and measuring steps or developing ways to reduce stress. So this is a cost that get trends that we basically have been talking about. Issue is how do you reduce this? So Intel is actually showing lower cost per transistor at 14 than we spend then compared to 22. And of course part of this architectural issue, part of it is a lot of process control. So there’s still several ways allowing this transition so you can get this technology into high volume.
So the key challenges in the industry right now, how to run 20 nanometers. We do have little challenges versus 28, parametric deals are lower. So in our opinion this is a major opportunity to reduce leakage. Also stress is an issue. How do you manage stress? That’s another opportunity in our opinion for Ultratech.
Then basically we have around some 20 nanometer impact. As I mentioned, Intel is delaying their roadmap, but they’ll bring it out. So again, leakage control, inspection is very time consuming. When we look at the wafer cost a key part of wafer cost is inspection cost. And then, how to continue the NAND scaling, how to continue DRAM scaling because the industry needs lower cost and high density memories.
So the conclusion is, we’ve had in effect low growth or negative growth in 2011, 2012 and also early 2013 by the industry spent. I mean we still have pretty large CapEx. Maybe they are downsizing, but the industry is still spending on new technologies. The memory market has experienced some growth because of management of capacity. So if you look at DRAMs you have three companies; you have Samsung, you have Micron and SK Hynix. We think that in many of the areas you’re also going to get consolidation and when you get consolidation the end customer pays a higher price for the industry guessability [ph].
As I mentioned, we do expect positive growth in 2014 and then somewhere between 2014-2020 there will be a motivation, I mean the industry has never gone a significant amount of time without a downsize. So that’s probably going to be 2018, but again we’re not clear on that.
We do see the migration, as well feature mentioned, being critical. We also see the need for more capacity. I mean if you look at the demand for memory, you need more capacity. If you look at the number of smartphones, you need more capacity. If you look at image sensors, you need more capacity. So the industry cannot rely on the capacity that’s in place. So it’s going to have to build capacity.
So again we do see the 20 nanometers, I mentioned, delayed by about 12 months from the early projections of foundry vendors. And again, they tend to be very optimistic because they want all customers in, but they are spending right now on 2014. So even though we think there could be delays they’re spending the money.
Then, as I mentioned, 3D packaging. Multi-chip packing is a way to frankly reduce the pressure to smaller feature dimensions. So we see a number of companies right now developing new packaging technologies and we think this is going to be an interesting area for segments of the industry going forward. We are not very positive on TSV by the way. We think TSV for high pin count to high cost, but there are other 3D packaging technologies coming in.
So from a semiconductor point of view we do see the globalization trends. We do see Asia coming up very fast. We are working with one Chinese governmental organization or have 80 billion RMB, $16 billion to build capacity in China. And again, this is for support of smartphones, the automotive industry and LED lighting.
So it’s a tough environment right now. Technology expenditures are increasing, but again for the next few years we generally are quite positive in terms of the total industry. Thank you very much.
Unidentified Company Representative
Okay. So Henri [ph] has taken about the macro environment of the semiconductor industry. I’ll talk about the latest development and the latest technology. There are four topics I want to cover and first I will discuss the Chinese film head and then talk about the laser fabrication in FinFET and FinFET device. After that I will discuss the memory application and some other opportunities.
I’ll start with the logical device [indiscernible] and today Intel is already in FinFET production and rest of the world is still using the fan-out technology moving to the 40-nanomter node. All the major franchise will move to FinFET and the FinFET technology is expandable to 10-nanometer and 7-nanometer, while the internal material will be changed to enhance the mobility and the performance. And at 5-nanometer and below, FinFET with three, five compound materials will emerge and there’s also other populaces such as nanowires or kind of that, which are also other opportunities. And as you can see, people getting roadmap is enabled mostly by the new materials and also new structures and that being we see the scales getting closer and closer to the accounted scales, which – what this all means is that the precision process control material and surface engineering, some of us in the management will become even more critical going forward.
So as device scales we see the number of LSA applications increases. Here I list the common device applications and they can be grouped into three areas [indiscernible] which includes the expansion and restructuring. These are the standard total activation staffs and the message that they expect at meeting where you can apply the laser annealing after high phase calculation or after the metal value calculation to improve the assumed properties. And the third area is the contact annealing where the LSA can be applied to form the clear site or for intake engineering to lower down the contract resistance. So as you can see, LSA not just for doping activation, it also can be used for material properties on occasions and also material synthesize.
So for advancing that the biggest challenge is the parasitic. Parasitic resistance, parasitic capacitance and the parasitic review will get worse for every dimension of that going forward. Our modeling shows that the parasitic resistance is going to double when you scale from 40 nanometer down to 7 nanometer. So you have to adjust that. Industry has to need to use multiple approach including the selective iffy, interlace engineering, conformal doping and metal annealing. And if you look at the component of the parasitic resistance, the major ones are expansion, resistance, sorting resistance and contact additions and laser can improve all of these components, and as a example I show the use of laser for silicide formation and increased contact resistance reduction.
For FinFET the industry is shifting from the nickel silicide to high silicide to lower down the leakage and lower contact resistance. The process window of the tight silicide compared with nickel silicide is going to narrow, which means that temperature competitive requirement will become more important and LSA is a lower patent density effect and tight temperature control will have advantage over our competitors doubling that.
Another way of the increased resistance is to use income plus LSA to modulate these dopants profile at the interface to lower down barrier height and this step can done either before the formation or after the formation and so you have lots of alternatives for LSA to play out low in lowering down the contact resistance. As I mentioned earlier, the material modification and the surface modification is going to be important going forward. And one example is the advantage of that annealing. Here LSA can be used to improve the interface vastly and can more divide this mix or reduce the total diffusion and result is a reduced leakage that has scalability or improve the reliability.
Another term we see is that for the month’s device we also need to lower down the thermal budget and the late-stage of the process. In the commencing of Gateway’s project the [indiscernible] which using high temperature is down after the debt and this causes the liability issue. So we assume that flow, the case that his host sequence is weak, the case that is down after that in turn. So this is where you improve the reliability of the case, but on the other hand it will cause the growth of the activation problem. So to improve that there are two ways you can do that. One is using LSA to replace the RTAs to minimize the total budget and also minimize the activation. The other way is to use an additional LSA staff out RTA for dopant deactivation. So compared to the flash annealing LSA has faster coding that reflects because of the localized cheating and 3D through these patients, which means you have less deactivation and better performance.
So this is the testing that 3D structure will cost a shadowing effect when the laser incidence at large angle and this in not correct and the shadowing effect is the problem for eye in computing, but not for LSA. So two reasons for that. First, the LSA use a very long waver laser and is a 10 micron. 10 micron is a silicon string, essentially transparent. So you won’t have any shadowing effects.
The other reason is that the grouping of the LSA is much, much larger that are being sized. It’s about 1,000 times larger and as a result – and it’s more variations in optical adoption can be effectively moved out by the key diffusion. And all this has been verified by the customers. In fact today LSA is in the baseline compact flow at a multiple customer site. Okay then on 10-nanometer, we think that with high end mobility channel we have come out and this material will be glow on top of the silicon and the structure are matrix tables because of the large initiatives mismatch. The material that has the high mobility such as [indiscernible] they are also market to the thermal projects and so the thermal stability overall is going to be a big issue for the future device.
For example, to be using RTA to a new high grade on top of 35 compounds at high temperature the 34 compound will start to disassociate and that was a great interface and mobility. And using LSA you can go to much higher temperature, result a grading in the interface and mobility. So we believe that going forward below 10 nanometer LSA is going to be essential for doping activation, content activation and high [indiscernible].
So next I want to talk about the memory application with DRAM adopting is slower than effective due to widened technology gap, mostly driven by the cost concerns. Historically DRAM reflow technology lags behind the advanced technology about six years. But this gap has increased to about 10 years recently and mainly is a cost content. For example, the [indiscernible] has introduced a 90 nanometer node, but today the DRAM makers still have not incorporate that yet, and similar situation applies to high-k metal gates.
Now, one thing those point out is that, if you compare all the costs, the implementation of millisecond annealing is much less than the thin silicon and high-k metal gates. And also when DRAM shrink from the 2x node to 1x node, we see that the device thing is going to be increasing during LSA. So, the overall performance cost will be more attractive when shrink down to the 1x node.
Another big opportunity is the 3D NAND and as you’ve heard from [indiscernible] already, Samsung already announced the 3D NAND based solid state drives and the 3D NAND sales bisecting more layers in the vertical direction, one of the big challenge is over here is the increase of resistance as you increase that height, which will degrade the cell currents.
To improve that high temperature anneal would be needed and the conventional melt technology use this single pole which have very limited heat penetrations and we use the solution both melt and non-melt, which gives you much deep heat penetration and more uniform heating across the whole set.
So we think that this is a very promising application for the laser technology going forward. Now the 3D technology is not just limited to the NAND membranes they can also provide alternative skidding path for the future ICs. Commenting on those skiddings relies on the level of shrinking enabled by metal. But as the cost of metal skyrocket the spontaneous skidding approach it’s following the third dimension becomes more attractive, and there are two packets, one is through the chip stacking the 3D packaging. The other is through the 3D monolithic integrator.
In the latter case, the lower thermal budget process enabled by the laser technology will play a key role to copy which was along the processing of top layer to affect the lower layer device. So this slide summarize the target device application for the laser, and to meet the various application needs, we have developed a suite of laser tools, that covers a wide range of process stages, from millisecond to nanosecond, non-melt to melt and single beams to dual beams.
And so we believe that going forward the LSA will be extendable to future advanced logic device, all the way, it down to 5 nanometers and there will be a great growth opportunity in both memory and future for VoIP. And finally I want to point out that currently laser process is still at the early stage of the growth curve. Thank you.
Unidentified Company Representative
All right, so I’ll give an update on the laser processing market. Here is an outline of my presentation. I will give an update on market status and drivers. And then talk about our laser processing product roadmap. I will go over a little bit of a competitive comparison and then summarize. So just a summary of where laser, the LSA is in terms of the market status, right now we shipped about 70 laser systems to the field since and that’s starting in about 2005, when we shipped our first tool.
In 2012, our market share was about 60%, and that’s the millisecond annealing market shares, so that account flashing annealing tools and other laser annealing systems. As far as production goes, we used all the major logic foundries and our wafer volume has doubled over the past 12 months, mainly due to the 28 nanometer round, now as far as development goes, we are in the sub 28 nanometer baseline and multiple logic customers for not only U.S but high-k anneal and on [indiscernible] applications, so we are in a very good shape to take advantage of the 20, and sub 20 nanometer ramp.
We’ve now shipped multiple LSA201 systems for the sub 20 nanometer development and the LSA201 is our ambient control system and I’ll talk a little bit more about that later. And then regarding 450, we have been selected as the 450 mm millisecond anneal tool for the G450 C Consortium and we’ll be shipping that tool in December.
I saw this chart, Art showed this, this is a foundry revenue forecast by technology node. So just a couple of points, I want to make here 28 nanometers of course, mostly the ramp is mostly done here. So we will see a few orders here, but not too many more. 20 nanometer is going to ramp; we know that several foundries will ramp 20 nanometer next year starting next year. In fact pilot production is pretty much is already starting at this point of time.
So we see that happening, but it will be as Art said a smaller node that seems to be the consensus. But the big, bigger node will be here 16, 14 nanometer FinFET and the big question is the timing and of course that all depends on the yield learning curve, but as Art and [indiscernible] said it looks like everybody is going to be buying equipment for this node and getting ready for it. So it looks like, next year there will be production starting on FinFET, probably in the later half of the year. But maybe even some starting in the beginning, in the first half of the year. So it looks to us like equipment will be – there will be money spent on 14, 16 nanometer next year.
So and I’ll show you a process of record matrix for millisecond anneal versus node later, but and you’ll see that basically LSAs in certain multiple steps for FinFET at this point in time and so we’re in very good shape to take advantage of this ramp in FinFET.
Now if we look at our revenue breakdown by node in 2013 and then projected for 2014, it looks like this. So in 2013, about a third of our revenue came from 28 nanometer orders and then almost half came from sub-28 nanometer orders.
Now if we go over here, and look at how that changes in 2014, there is a quite dramatic shift in fact over less than 10% of our revenues going to come from 28 nanometer orders in 2014, about 40% will come from 20-nanometer and then for sub-20 nanometer over 50% of our orders. So it’s really a pretty dramatic shift and it just shows how our LSA revenue, LSA is really completely driven by leading edge technology node.
Now this is a millisecond annealing process of record matrix. So what I’m showing here is for basically five of the foundries for each node, starting with 30 to 28 and 20, 16, 14, how many millisecond annealing set are in, are inserted as the process of recording each one of those nodes. And this is all millisecond annealing, for flash annealing and the other laser annealing sets.
So I will go through every cell, but basically one of the main points I want to point out here is that, there is this idea that’s been kind of floating around, I think the analysts community that millisecond annealing is not required or not needed for FinFET at 16, 14. And that is not the case at all. As you can see from here, that you have anywhere from one to five steps being used as 16 to14 nanometer for FinFET, and a lot of those steps one you described ultra-shallow junction one or two steps, high K anneal, titanium silicide, reactivation.
So there is a really intensive use of a millisecond annealing for FinFET and it’s really, we consider it in enabling technology. And a lot of that is because as you scale down, device nodes, you really need lower and lower thermal budgets and we could do consider this to, this will trend, we’ll continue with 10 nanometer, as you change the channel material, the silicon germanium, which can take even less thermal budget, so the trend will continue beyond 14 nanometer.
Now, I said this is all millisecond annealing, but just to give you some flavor of how much of this is LSA. There is 40 process steps here in total and LSA has 32 of these process steps. So 80% of these process steps are captured by LSA.
So this is our laser processing product roadmap, and so the LSA101 has been our flagship product for the last three years, is what’s been mostly used for the 28 nanometer ramp that I spoke of earlier, where we doubled our wafer volume over the last 12 months it’s a what we call an open architecture for the wafers exposed to air.
Now we earlier in the year, we introduced the LSA201, where we control the ambient or the gases that are the top certain for the wafer is exposed to, so full wafer ambient control and that enables processes like high K anneal, titanium silicide et cetera and this really allows us to expand our application space and enable new processes.
We are going to ship our 450mm tool by the end of the year, as I spoke off, that will also be an ambient control fluid only. And then later on next year, we will introduce a new tool that we call LXA and [indiscernible] refer to it towards the end of this talk, but basically we are going to take now that thermal budget that we are doing now which is on the order of a 1 millisecond and shrink that time scale by about factor of 1,000 and go to the time scale of say 100 nanoseconds.
And that gets back into this idea of shrinking the thermal budget. So we’re going down by orders of magnitude, in order to enable new processes and really increase the extendibility of our LSA product lines down to 10, 7, 5 nanometers, so really this product roadmap will take us all the way down, basically as far as we can see which is a 5 nanometers.
Now before I go into this competitive comparison I will say I thought it might be useful to take a quick look at the history of laser processing, development of Ultratech, so this goes back to 1994, and all the way up to 2013, and the idea here is to give you some idea that the long and deep and really the commitment of Ultratech to bringing laser processing to the semiconductor industry.
So in 1994, Ultratech acquired some key patents from a technology – a laser technology called [indiscernible] from Lawrence Livermore Labs and that’s what really initiated our laser processing programs, and throughout the mid-90s, Ultratech is work on melt laser annealing. It was a little bit early for melt, so in 1999, we began sub-melt technology research and that really led to the delivery of the first LSA production system in 2005.
Then that put into production in 65 nanometer, high performance technology node with the LSA 100, then in 2010, we introduced the 101 which was a high throughput version along with many other improvements. But a big jump-up in productivity with the 101 and then if we get forward now to 2013, the next product that we introduced was really the major product was – as I showed in the roadmap it’s a 201 ambient control, and then the next one will be LSA.
The one box here showed, which is not LSA is here in 2003, and I’ll come back to this later, but I didn’t want to mention that in 2003, this is the delivery of the first flash anneal system to a major IDM, and that was a couple of years before, we delivered our first LSA production system, so I will come back to this later, in the last slide so just to make a note of that please.
One thing I also want to mention is that throughout this long history here of laser processing. Ultratech is now over 900 patents in all of its technologies, but over 200 patents in laser technologies, which is, I think, pretty impressive.
Now just a few slides on competitive comparison and some of the advantages of LSA compared to the other competing technologies, this is just a schematic of LSA and the LSA is really – the heart of LSA is the CO2 laser, carbon dioxide, gas laser which has a long wavelength of 10.6 microns. If we compare that now to the wavelength of flash lamp anneal, which is in this area of range of 0.5 microns to 0.8 microns, you can see that it’s over 10 times longer wavelength than a flash lamp.
And if we compare to a diode laser annealing system, again that’s a similar wavelength range to the flash lamp, so it’s again, over 10 times longer wavelength. And we also bring our laser in at this special angle called Brewster’s angle and really what that does for us is allows us to have minimal pattern effect.
Now I’ll talk more about that in a couple of slides. If we compare that now to a flash lamp and diode laser, that short wavelength actually generate – large pattern effects in the flash lamp and even more severe pattern effects for the diode laser. And so essentially, going over to the diode laser, these severe pattern effects are really what has prevented the diode laser annealing system, some penetrating the front-end and it’s really limited to nickel silicide applications.
Another advantage of LSA, which I’ll talk about in the next slide is that it’s low stress compared to the flash lamp anneal, which is a high stress. Basically these lamps coming down hit the wafer all at once, with all of the energy in one millisecond and creates thermal shock and breakage issue, and we've close loop temperature control which is unique to our LSA system. And so with the LSA system you can use that for both front and middle of line.
The other thing I should mention about the flash system is that you got basically its got four within wafer uniformity, it’s very difficult to control all of these lamps at the time and get very good uniformity across the wafer, whereas as LSA with the close loop temperature control, you can achieve very, very tight within wafer uniformity.
So going on to talk a little bit more about the stress advantage, this really just comes down to quite simple physics. Where with the laser you are just heating up a very small area of the wafer at any given time. So this shows the beam on the wafer and this is actually a simulation of the stress field around the beams. So it’s very localized and you are just scanning back and forth across the wafer. So at any given time, you are only heating up a small portion, you are only putting in a small part of the energy and you are putting in the energy of the wafer over the course of say about one minute.
So the energy from the – strain energy from that beam can be dissipated in three dimensions to the rest of the wafer and then that energy can in turn be dissipated to the chuck where the wafer is held down by vacuum. So it kind of glides along like someone swimming through the water. If we compare that to flash, you are basically depositing all of the energy at one time within about one milliseconds, compared to say one minute and that is really what causes a thermal shock.
And the wafer just sits on – its free standing on pin, so there is nowhere really for the energy to be dissipated. It doesn’t have a chuck that the energy can be dissipated to. And the wafer actually when the flashlight lamps hit the wafer, it actually bows up during the anneal by at least 10 millimeters. So this is what really causes the thermal shock and causes the breakage. So it’s just a very different physical process the way we put the energy into the wafer. In one case, it’s low stress, in the other case you get that high thermal shock.
As far as pattern effects go, again the wavelength is the key here; in our case we have a very long wave length. The wave length is very long compared to the film thickness on the wafer, and it’s also very long compared to the height of the fins, in a FinFET and long compared to the spacing of the fins. So basically when this light comes in, when those CO2 laser comes in with this long wavelength, it’s almost as if there is no patterns there at all and this is measured reflection state of a real die and you can see that’s it’s very, very uniform and it results in a temperature variation within the die of about 10 degree.
And as Yun was saying there is really no shadow when you’re light trapping by the fins. If we look at a short wavelength either flash anneal or LSA that short wavelength light that can get trapped inside the fins, it also can create interference effect in the film and what you end up with is a non-uniform absorptions within the die from the different – basically the different pattern densities created by the circuitry that is imprinted on the chip and you can end up with temperature gradients or temperate variations that are more than 100 degree.
So you say, why don’t you care about that? Well, what this really can do is means that transistors on one part of the chip can function – have different performance than transistors on the other part of the chip, this can hit your overall electrical performance of the chip and your yield. So it can be a very serious issue. And so as you can see here pattern effect in LSA can be over 10 times smaller than you have on either flash lamp or dial laser annealing.
So last slide and the competitive comparison, I did want to show the market share evolution comparing flash lamp anneal to LSA, so if we look now to 2003, this was before LSA was introduced so flash anneal was introduced a couple of years before LSA, and so flash anneal for these 2003, 2004 had 100% market share now this is a market share just for the front-end. But now in 2005, when we started to introduce LSA, now you can see flash anneal’s market share starting to erode, LSA starting to come up and it’s been more or less a continuous erosion of the market share, to the point were in the last three years, we’ve had in the front-end about 80% market share compared to flash. So we take this as validation of the general advantages of LSA compared to flash lamp anneal giving better device results, better yields and you can see the adaption of LSA here accelerating over the course of the last 8 years to 10 years.
The other very important point here about LSA is that, we are working – we – our productivity is very important for us, so if we look at costs of ownership, flash anneal at 25 wafers per hour. LSA201 or latest model is at 35 wafers an hour. So we have some cost of ownership advantage here. But right now we are introducing throughput improvements to take us to 60 wafers an hour and customers are starting to adopt this now and into next year, and at 60 wafers an hour, you can see that we have a very significant costs of ownership advantage and at that point, I think that flash anneal doesn’t really have any advantages left. Any potential advantages left and that’s should put us in even better shape competitively.
So to wrap up, LSA remains the market and technology leader in millisecond annealing, I talked about some of the advantages of LSA which has made us – given a flat position, minimal pattern effects, low stress and I think those advantages becoming even more apparent when we go to FinFET.
We are in a good position to take advantage of the sub-20 nanometer ramp or in multiple steps to 20 nanometer with sub-20 nanometer technology node and 20 nanometer is going to ramp – it’s starting to ramp now, we will ramp through 2014 and FinFET will start in the back half of 2014. And our road map really, ensures that we have the flexibly across the front-end and middle of the line processes and ensure that’s we are extendable out to 10, 7 and 5 nanometer. And the LSA201 with an ambient control, we feel is the most extendable millisecond anneal platform on the market now, and we will really allow us to take advantage of some of those new applications that Yun talked about such as film modifications processes, so with that I’ll wrap up, thank you.
Unidentified Company Representative
All right, I hope everyone is enjoying your lunch, we are going to change gears here a little bit from laser processing to our inspection system. I’m David Owen, I’m the technologist for the Inspection System. So let’s just start with a quick overview of what is this Inspection System. So inspection can cover a lot of things, specifically what we’re talking about is a system that inspects the wafer for stress deposit be in distortion. So the primary applications for this are in lithography control and yield management. I’ll be showing you some examples later.
And from a production standpoint, this technology is unique and that it allows high-speed comprehensive wafer backing. So we can generate over $3 million data points on the wafer with throughputs greater than 75 wafers an hour. So just to give you a point of reference, typical metrology and inspection tools in the fab run somewhere 40 and 60 wafers an hours kind of typical. So, comprehensive data in a short amount of time. Down here in the lower right hand corner you see example maps that we can generate using the system of either typography distortion or stress.
So I’m going to give you a brief overview of what the technology is, how it works, then I’m going to talk about applications, specifically those around lithography, and around yield and device performance control and enhancement, and then I’ll summarize. So, just as a starting point, even though this product is new for Ultratech, we announced this event last year, and we’ve been shipping our first systems this year. This technology has deep routes.
So really is over – almost 100 years ago, the kind of the precursor of this type of grading interferometer was developed. And these types of interferometer have been used in optical wafer on testing for a long time. So, although we have a specific implementation of this, the concept about taking a set of gradients as I’ll show you in a moment using them as a interferometer and measuring something of interest has been around for a long time.
So, my involvement with this technology started when I was in Caltech a while ago. The development of this technology pre-dated my time by few years is in the late 80s, but this technology was developed and has been using 100s of academic papers. It was really kind of in the late 90s that we started applying it to the study of stress and distortion in thin films, wafers, et cetera, it was a work that we did with JPL and that led in through 2002 to the foundation of a startup company that tried to productize this.
When we transitioned over to Ultratech in 2006, 2007, we developed the next-generation system, which allowed us to go out to customers and do data evaluations, which gave us the confidence to data and understanding of the customer needs to introduced the super fast system that I’m talking to you about today. So, essentially we’ve taken all this learning from – with this particular technology over 25 years and rolled it into a system that’s suitable for high volume manufacturing.
So how does this technology work, you will essentially see large interferometer, and I don’t expect that anyone in here is an interferometer expert, but let me give you a quick overview of how this thing works. So, if we start with the wafer here, we send in a huge laser beam a 300 millimeter diameter laser beam that essentially takes an optical imprint of the wafer surface. So it starts – the laser starts out flat, ends up distorted because of the shape of the wafer. We pass that distorted laser through two parallel defraction gradients, gradient 1 and gradient 2. And what the gradients do is really just create copies of this distorted wave front. So just think of the gradient as a copier and what we do though is that by the time that the copies pass through the second set of gradients or second gradient, two of them interfere with one another, so that’s the interference.
So essentially we are taking one copy of the beam another copy of the beam and we are just interfering them one with the other. But that’s done with small lateral offset. So the distortion of the laser gives you information about the wafer height, the shift is an offset in lateral distance. So you all remember geometry, change in height over change in distance is slop or tilt on the wafer surface. So we have a large field interferometer that essentially measures how tilted or sloped the wafer is at every point on the wafer surface.
So that’s essentially what it is? What’s unique about this compared to other interferometers is that its self referencing, most interferometers rely on an optical reference surface to understand what the shape of a optical wafer is. This is self referencing. There is no external reference. We’re referencing the wafer against itself, and that leads to a series of technology advantages, and I’m not going to read every cell in the slide, but the fact they where self referencing means – self referencing imaging the whole wafer and use some other techniques means that we get, high accuracy, rapid data acquisition on pattern wafers, which is what our customers want to measure.
And adds a whole lot of benefits for the customers in terms of low COO, high fidelity of the measurement, able to trouble shoot it et cetera. And a key feature of this is – this technology is scalable and extendable so we can readily scale up to larger wafer sizes, different wafer types, without severe technology innovation required. It’s more about engineering not about invention or innovation. So like LSA we see a roadmap to extend this technology into the foreseeable future with the next technology nodes
So that’s it on the technology, so now let’s move to the applications. As I said upfront, we are going to talk a little bit about lithography and a little bit about yield enhancement s. There are some other applications that we’re in the process of developing, that’s I’m not going to talk about in detail around stress control for TSVs and focus control for lithography, in other words understanding how wafer shape affects lithography’s ability to focus and print features, but right now we are just going to focus on the overlay control. Using inline monitoring of process induced overlay errors and using that data to either to feed for that correction to lithography, I will describe that how that works in a moment.
With yield enhancement we can use stress as a metric to understand essentially where in the process flow device performance variations come in, where yield loss occurs, and I’ll show you examples of that as well. So kind of fundamental to this is the idea that we can shape any process flow from wafers start to fab out, and make our measurement. And so in this way whether it’s a film deposition anneal edge or strip, we can tell a customer what a particular process is doing to its wafer in terms of typography stress and distortion. So there’s no limit to where this can be inserted inline, what types of problems it can be used to diagnose and characterize.
And again, that’s very unique from a metrology inspection standpoint. Many inspection steps are limited to specific points in the line, because they do specific things in a very limited type of way. But we have this ability to look at anywhere in the process flow and help customers understand where the problem comes from by characterizing every step of the way.
So with respect to overlay, what’s happening is that, you look at IGRS [ph] roadmap and the overlay budget is shrinking as you go form last generation 40-nanometer, 45-nanometer, current volume noted 28-nanometer and 20-nanometer and below, we’re seeing this factor of two or greater decrease in the overlay budget. But at the same time, the wafer shape, how much the wafer is distorted when it gets to litho tools is becoming a larger and larger percentage.
So we have our leading edge customers tell us for their advanced technology nodes that for some critical steps up to 50% of the overlay budget can be consumed by that wafer shape and distortion. So that doesn’t matter how good the lithography tool is, how precise the radical is, if the wafers are messed when it arrives at the lithography tool, there is no hope.
So understanding how to characterize this component of the overlay budget and more importantly, how to control it is very critical. So how does that implement. So for our tools, we demonstrated in three different settings that we can correlate our measurement of wafer distortion to traditional overlay.
So here is a part of overlay versus our displacements or distortions, again, both these graphs are on the nanometer scale. They’re several nanometers; you can see a good line of correlation; high correlation coefficient. So what does this number mean is essentially that greater than 90% of the overlay variation in this side of experiment can be traced backed to process in these distortions et cetera.
So we can use this fingerprinting to understand wherein the process flow, those distortions are having the biggest impact on overlay. So we can go back and say okay, the wafer was distorted when it got the lithography where does that come from. So a typical implementation might look something like this.
You can get two litho steps: litho 1, litho 2 and a series of processes in-between. Typically what happens is that you don’t do – again, right now, no one really looks at what’s happening with these process steps. so when the wafer gets the litho, they use traditional overlay methodology and feed that information backwards to try and correct four or six what happens to the wafers.
But by the time, the wafers have gotten here, it’s too late. What we can do with Superfast on the other hand, its measure what happens to the wafer between litho 1 and litho 2 and feed that information forward. So we can use it in a proactive way, to understand how to correct our wafer shape evolution during the process for us. and yet another implementation is just use it simply as an upstream is inspection. so if you identify any one of these particular steps has been the critical step, you can just set up inspection at that particular step and understand what limits of wafer distortion we have to maintain to be able to be successful at lithography.
So the next slide is actually a customer use case. This is one of our first adopters of the Superfast system. This is how they’re using a tool. They know they have an out-of-spec overlay issue, the catching of lithography. By the time, you get the lithography, it’s too late. So what we work with them to isolate that problem to a specific step upstream of lithography. and furthermore, we’re able to help them characterize normally which step, but which chambers if this is a cluster tool with multiple chambers, which chambers in a specific tool were causing them problems.
So now, they can isolate it down to tools, chambers et cetera and implement and they are implementing our technologies after those critical steps to make sure that – what the wafers need that step. By the time, they get the litho, they should be okay.
So it reduces what we call the wafers at risk. If a problem happens here and in these high volume fabs, you continue to process wafers through and one week or 10 days later, you catch a problem at litho. You’ve already processed tens of thousands of wafers. We’re up, we’re letting customers discover that early, so they can reduce rework, catch problems before they cost them a lot of money. So that’s the basic value proposition.
So we cannot apply a same type of use case in RFI and the same type of use case to performance and yield. Again, do the process fingerprinting and understand how these different process steps correlate to yield. So this part, which I’ll talk about a little bit one, the next slide shows, the yield probability as a function of stress. So in this case, as stress is increasing, yield is increasing.
So much in the same way, we can identify those critical processes upstream, which process steps are causing these problems, and then set up a monitoring scheme. So again, customers can catch that problem early. So exactly, how this yield correlation looks this year. So again, this is a part of yield probability. so up here is kind of the baseline yield of this particular line in this particular device, but you can see a different process steps; process step 1, process step 2 actually.
As the stress increases, there is kind of a critical stress above which, you start to see a pretty significant drop in yield. And again, this is well upstream of our fab out. So now they know that, if they have stresses above this threshold for this process or this process that they’re going to have a yield loss, so a higher probability of the yield loss associated with that. So again, it’s very easy to pick out the fast – steeper this drop-off, the higher the stress sensitivity. So if this curve was flat, we wouldn’t – there would be no impact to stress.
So we can look for those process steps that have this steep drop-off in yield with stress and say okay, here is a problem, here is a problem, here is a problem. Let’s go back and help you monitor that and potentially, fix it as well. So it’s very powerful in that respect. So again, we have this clear effect of stress on yield, we can use this fingerprinting to develop a yield-based model, basically for whole flow.
So any point in the process flow, we can tell you what the probability of the given device yielding is. And we can isolate issues whether those are issues at the edge or issues that are chamber-to-chamber as we have in the previous example with overlay.
In the past, we’ve also done studies where we correlated stress to leakage directly, so as Handel said earlier, leakage control and management is kind of a critical factor that needs to be addressed in the advanced technology nodes. So we’ve done the work where we’ve characterized by device stress variations throughout the process and compare that to leakage loss at the end of the line or leakage variation.
And we can see pretty clearly, just comparing these two maps that low stress in the center corresponds to low leakage in the center, higher leakage on the edge is tracks with higher stress on the edge. So the two of them leakage versus stress correlate very well, such that 77% of the leakage variation in this case can somehow be trapped it back to something we can measure with our stress methodology.
So with that, I’ll summarize. So in the past year, we made significant progress with growing interest from both logic and memory customers and implementing this technology in advanced manufacturing again, with applications in both overlay controls and yield enhancement. because this – the uniqueness of this superfast inspection system, we’re able to generate comprehensive data, millions of data points, very quickly and look at issues within wafer, wafer-to-wafer and tool-to-tool. And again, this is something that Handel said earlier; future devices will benefit significantly from active to photography and stress management. So whether it’s lithography, sorry lithography or yield and performance, these are things that we can catch stress and distortion are leading indicators of performance yield and lithography issues.
So thank you very much.
So I’m Shri Shetty and I’ll give the market update for the Superfast 3G Inspection Technology. This is a quick outline of my presentation. I’ll give a very quick system overview. I’ll talk about the market drivers, what are the technology drivers that are generating the demand for this product. I’ll then give a quick product overview.
So I’ll talk about our product roadmap, what is our overall product strategy and what is the current status of this product. And then I will focus mainly on the overlay application. The overlay market is our target application and I’ll compare us with the competition and what is our strategy in this market.
So this is a quick system overview, the key differentiators are as follows: the core technology that is used in the Superfast product has been around for almost 25 years. Ultratech has had this product in-house for almost a decade now. We have over hundreds of papers that have been published using this technology and there are also numerous patterns in this space. So we are well covered in terms of patterns, IP, publication et cetera.
What does this tool actually do? The tool measures pattern wafers mainly in 3D. What I mean by 3D is that, we give you information on stress, distortion, topography in the X, Y and the Z directions. Typically, tools out there give you either high resolution with low throughput or low resolution with high throughput. We are unique in the fact that we give you lots and lots of data very quickly. Then the Superfast tool measures the wafer, we give you almost three million points of data on every wafer that goes to this tool.
The first system that is shipping out this year those have a throughput of around 75 wafers per hour. But I’ll show you our roadmap in the next few slides that we do have a clear part of doubling the throughput from 75 wafers per hour to 150 wafers per hour in the next few years.
We also measured all the way to the edge of the wafer less than two millimeters and we have, because of the high throughput, low cost, we have a very low cost of ownership. This technology is also, we believe is extendable to all shapes and sizes. So we do not see any technical barrier to extending our 300 millimeter tools to 450 millimeters, all measuring three dimensional structures like vertical NAND or FinFETs.
So the technology has been around for sometime. Why are customers pushing us right now to develop a technology that can up to that can measure this as ab in-line inspection technology, it mainly has to deal with what is happening on the wafers.
In the front-end, customers are adding many, many high stress films like silicon germanium, silicon carbide with EUV getting delayed, the foundries out there and the DRAM customers are going to double patterning, triple patterning and both memory and logic are going to three dimensional structures like FinFETs and vertical memory.
Customers like Intel are also pushing towards 450 millimeters. So if you think about a wafer, on the gate level, they’re putting customers putting many high levels stress films. They are adding three dimensional structures like FinFETs and many, many layers of lithography, and at the same time, are expanding the wafer side from 300 millimeter to 450 millimeter.
All these changes are happening simultaneously, which is making the stress, distortion, overlay issues increased exponentially on the wafer. If today, there is one issue in the three dimensional space that is impacting wafers, it is stress, which is why everyone in all the conferences, all technologies out there are talking about the stress distortion are focused on overlay.
This is our product road map. As I showed you last year, we do had – we had multiple data tools out there; one with a very large Asian foundry that did both memory and logic, and another is a very large NAND customer out there. We expected to swap these tools with our production tools this year.
Our first tool is coming out this year is the 3G system. It will have an initial throughput of 75 wafers per hour. Next year, we will be coming out to the 3G plus systems. The main difference between the 3G system and the 3G plus system is that to increase the throughput from 75 wafers per hour to 100 wafers per hour.
The changes in hardware and software are minimal and we expect we should be able to upgrade all the 3G systems that we shipped this year, can be upgraded in the field to 3G plus. We are also; in the future going to be developing a 4G system, which will have different hardware, it’s mainly the front-end, the 4G will take the throughput from 100 wafers per hour to 125 wafers per hour and eventually, there will be a 4G plus that will go to 150 wafers per hour.
The 3G will be able to get upgraded to the 3G plus. the 4G will be able to be upgraded to the 4G plus. we do not expect the 3 Generation System to be able to get upgraded to the 4 Generation System. In the future, we’ll be developing integrated modules that we should be able to take this system and integrated on to our LSS system as on board inspection system. we expect that will be around the same timeframe as when the 4G system comes out.
This cutting-edge technology typically, the technology is adopted by cutting-edge devices like logic and foundry, and DRAM and NAND come a little later on. the Superfast is unique, because of the technical drivers; I spoke about a few slides ago. we are seeing parallel demand from all four markets: logic, foundry DRAM and NAND.
This is our overall product strategy. Our target market is memory, foundry and logic. we expect to ship a few seed systems less than 10, globally, in 2013, mainly in both the memory and the logic markets simultaneously. the product development, we expect to want to ship the tools up this year, we expect to work with all these leading-edge memory and logic foundries over the next few quarters in customer application development.
The throughput as I showed you is, mainly driven by higher – our roadmap is mainly driven by higher throughput. We are also building infrastructure both in software and hardware locally in Singapore. this is our overall product strategy and lining up with our product strategy is our product status. we did – in terms of tool shipment, we did ship our first tool of the 3G tool out in Q3, this was shipped to a DRAM manufacturer in Asia and has been inserted in limited production. we will be shipping a handful of tools this year, as I said, less than 10 to the DRAM, NAND and logic customers out there, not all these tools will be revenue tools.
Few of these systems will be revenue systems and the rest will be on extended evaluation for customer development. We have other than these systems that they’re shipping this year; we also have received LOIs for, and multiple commitments and multiple systems next year. So all future production, the way we’ve designed this system is that the first few systems are being built in San Jose but all multiple systems and all systems next year will be built in the Ultratech Singapore facility. We have developed our manufacturing infrastructure and our support infrastructure such that all the support will happen, all the tools that we manufactured and supported out of Singapore.
We have also ordered some long inventory so that, that is not a bottleneck and we have hired and trained our technical support in Singapore this year, but Dave did talk about the different applications out there this technology can be used. We are actively engaged with customers on these four applications. Once the first and major application is overlaid this is our primary application. This is the biggest market and this is what we are focused on. We are also working with some customers in yield correlation, data monitoring and edge monitoring, but we believe that overlay is our primary market. This is the biggest market and this is what we are focused on. We will be shipping tools to these markets as well, but this would be the biggest market. This is the biggest market. It also requires the most works.
So some of our customers are focused on the overlay market and they will be looking at this later on while other customers are initially focusing on these markets and then we’ll be transitioning to overlay in the future. Either way, we expect that in the next year or so, our customers will test all these four applications and will be using the tool for overlay, but also using it in some subset of the other applications as well.
So I did say that overlay is our primary market. This is the overlay market size. EUV is getting delayed more and more. The last papers that are in publications are coming out of sale that is going to be sub-10 nanometer, maybe 7 nanometer and below.
As EUV gets delayed, customers in order to meet the gap, all the leading-edge foundries, DRAM et cetera are adding more and more lithography steps. As these customers add more lithography steps, it increases the overlay market significantly. Because it is doubling and tripling the number of processing and lithography steps in there.
At 40 and 28 nanometer, most of the leading-edge foundries are being single patterning and the market size was around 150 million. As we go to sub-28 nanometers 20, 14, 10, 16 some foundries are going to dual patterning, while other foundries are going to triple patterning. By going from single patterning to dual patterning, your market size doubles, because the number of steps just doubles, so you go from 150 million market size to 300, and if you go to triple patterning, it goes up to 450 million as we expect EUV continue to be a challenge, and this market to continue to grow. Today the only player in this market on the overlay metrology side is the KLA Archer. The KLA Archer has almost 98% of this market today. And this is the market that we are targeting right now.
So before I start, I would like to point out a fact out there, we believe KLA is a very strong company. The KLA Archer tool is the incumbent system out there. It has been around for maybe 10 years and it dominates the market today. It has almost 98% market share. We believe that we will not replace the KLA tool. We are a complementary tool to the KLA tool. The KLA tool today has some limitations that I’ll show in the next slide, gives you very low resolution, has high cost of ownership and has limited edge monitoring.
We believe that the customers because they had been using the KLA tool for so long will continue to use this tool, but will reduce the number of wafers that go through this tool and will start using it as a metrology standard. They will add us as an inline inspection tool as a complementary tool to the KLA tool. So they will be using KLA and us.
So we are not competitive. We are actually complementary. Going forward, we believe that the KLA will continue to be used as a metrology standard while they will start using us as an inline inspection tool. So they will use both, they will just continue to reduce, because the cost of the KLA tool is high. They will reduce the number of wafers going to the KLA tool and use it as metrology standard and use us as an inline inspection tool, there where we will get a majority of the wafers going through our tool.
What are the current limitations to the KLA tool? The number one limitation is high cost of ownership. The KLA tool is almost $2 a wafer. This is why customers right now are using this maybe and the limited sampling mode of few wafers is lot. The KLA tool requires special dummy targets on the wafer. The KLA tool does not measure the devices directly as device sizes are shrinking, these dummy targets and devices are behaving differently. So they can no longer predict what is happening on the actual devices.
In leading foundries DRAM, NAND, Logic, the edge of the wafer is very important. Today most of the yield loss that is taking place is at the edge of the wafer. The KLA Archer tool at 5 millimeter to 10 millimeters from the edge of the wafer has between 3 to 5 points. At 3 to 5 points, you can tell almost nothing about the edge of the wafer. The edge is very critical, that is where these foundries are loosing their money and that is where they want to focus on.
And last is that the KLA Archer tool has very low resolution around 200 points per wafer, which tells you what is happening locally, but does not give you any idea of what’s happening on the devices. If you compare them with us, our cost of ownership is much lower than KLA. I’ll show in the next slide that today our cost of ownership is half of that of KLA and with the 4G plus, we’ll be one fifth of that of KLA.
We do not need targets. We measure everything on the wafer including the actual devices on the wafer. KLA measures target, so we can tell the customers actually what is happening on the wafer, as we measure the actual devices. The KLA tool gives you 5 points at 10 millimeters, 5 to 10 millimeters on the edge. We give you thousands and thousands of points, at 5 millimeters on the edge of the wafer, we give you 70,000 points of data. This is a wafer from a leading edge foundry.
As you can see on the edge of the wafer there is very high stress non-uniformity. If you put 5 points out there, it will tell you absolutely nothing. We have been working very closely with multiple customers out there to look at the edge, because the edge is critical because that’s where a lot of these foundries are loosing their money. And finally they measure 200 points, we measure 3 million points of data on the wafer.
We are not competitor with KLA, but the reason I put this slide up there is to show the difference in cost. The KLA tool today is at $1.94 a wafer at 200 points. They measure 200 points at $1.94 a wafer. Because the cost is so high, the throughput is very low, most customers use them at limited sampling a few wafers a lot.
Our throughput for the 3G tool because that an inline tool is half of that of the KLA. As we increase the throughput from a 75, 100, 125 and 150 our cost goes down to $0.43. We expect the reason of our roadmap is driven by throughput and the reason we are trying to drive down cost is we want to make the cost of inline inspection as cheap as possible so that the customers measure us for as many wafers as possible in the line and for as many steps as possible in the line. So we are driving it down, so that we can try and get as many steps and as many wafers to our tool in these customer fabs.
This is a competitive summary, so the KLA Archer measures 200 points, we measure 3 million points. KLA Archer does not measure devices, they measure dummy targets. We measure actual devices. This is the differences in the measuring type. Typically they show the slide on this, KLA typically measures post lithography. We can measure anywhere in the line, pre-lithography or any step in the line. They have limited edge exclusion, which depend on the targets 4 or 5 points on the edge of the wafer. We have almost 70,000 points that measure all the way to 2 millimeters on the wafer. Their throughput is around 45 wafers for 200 points. We measure 3 million points between 75 and 150 wafers per hour. Their cost of ownership is $1.94. Our current cost of ownership is half of that and we expect to be one fifth of that in our next-generation tools.
So quick summary, our benefits are mainly – we give you lots of data, very high throughput, lowest cost of ownership, this helps our customers reduce [Indiscernible] work, reduce breakage and tighter device control. These are all the applications that we are currently working on, feed forward for overlay, topography measurement, high stress processing, device parameters and tool matching, wafer monitoring in the line. Thank you.
E. Jan Vardaman
Drivers for some of the advanced packaging markets today. So I’m the President of TechSearch International. We are a company that does consulting work. We’ve been in business for 26 years. And so we’ve been around and seen a lot of changes in the industry over time.
And so one of the things that we see happening in advanced packaging is lot of the flip-chip growth and we see that as around 25%, if you include everything from 2012 to 2017 in terms of unit. This is including all the CPUs for a personal computer, ASIC field programmable data array, DSPs, chipsets, graphics, digital TV and other media product, set-top boxes and things like that, and a lot of things like diodes and filters were also counted in this number.
Now one of the things that’s happening right now is this trend toward copper pillar and that includes the things that I’ve talked about earlier, as well as the micro bumps for the 3D ICs, a lot of those are copper pillars with a little solder cap on the top.
And a lot of our future drivers right now for our flip-chip of course are things as you might imagine in the wireless market, which is like a mobile phone, our tablet, things like that. And that’s really driven by both the form factor and the performance and these are things like the base band processor chip, the application processor, the bottom package and the top package for example, which is a package on package, a 3D package stacking.
That’s where you’ll typically find an application processor in a lot of our smartphones and when we look last year in 2012 about 90% of those were flip-chips still about around 10% or so well bound, but kind of moving up in that direction.
And so we typically see some of what has been like a thin silver bump migrating toward this copper pillar that will either have a thin silver cap on it or little tin on it. So that includes everything like all the Intel stuff, a lot of our products in Qualcomm are now migrating to copper pillars and things like that, so it’s a good growth.
So I like to call this copper, copper everywhere and that includes things like sometimes the thick copper pad even. And, so we are kind of at the transition in our industry like we were when we went from the evaporated bump type through the new technique bump type and so we’re making this next migration.
Now the only hiccups are things like, and one of the reasons that we’re doing this migration is because people are going to finer and finer pitches. So what I like to tell people when I give this talk is that the bump is the easy part. So the people have to assemble this and remember it’s getting finer and finer pitch. Even though that has a little solder cap, it doesn’t have the same self-aligning capabilities that we’ve always been familiar within the flip-chip industry
So traditionally, we’d use a conventional process of fix the die, place it, reflow and bond it in like a big oven. But now where that’s really limited to 140 micron pitcher sub, we’re going to be finer and finer pitches as we done into these next technology notes, but when you get to things like 100 micron pitch or even some of the 40 micron pitch staggered bumps people are using the copper pillar as a fine pitch, and they are going to have to use a different assembly technology. So a lot of people have looked at our thermal compression bond, which means that people would put a underfill material on the substrate, put the chip down and do the reflow and the bond and the underfill cure all at the same time.
Now that sound’s really good except you have to have a lot higher placement accuracy and precision bonding with that like plus or minus 2 microns and that’s a lot more difficult and it’s also a much more expensive piece of equipment, so and your throughout is a lot slower. So these are driving – there is a lot of changes going on in our industry so that’s kind of the difficulty with this movement to the bond pitch with chippings and copper pillars.
So remember if you were here with me last year I told you that the phones were getting thinner and thinner. I’m here to tell you that they are still in. Now you know as well I do that you don’t have to have a super thin phone to make it work better. It’s just that it is the fashion thing, here we are in New York, it’s fashion, is what drives a lot of this mobile industry thinning. So your thick phone will work just as well, but as you can see we’ve progressed over time. The consumer preference is really thin product. Now that’s still driving our packing people crazy, because in order to do that you’ve got to have a really thin packaging size. So for that reason, we’ve seen a continued trend toward the adoption of more wafer level packages in these phones. The latest iPhone 5S that came out is according to chip works, they know we can tell – it looks like it has about 18 wafer level packages. That’s another big jump in wafer level packages and we expect this trend to continue because that’s really a very low profile package.
So while we’ve already converted a lot of devices to wafer level packages in the phones and how we got those thin things to begin with. We are still being driven by the smartphones and tablets to continue that use of package. And so our estimated growth rate of around 11% in terms of units from 2012 to 2017, and so we’ll expect that to continue.
Now for some of those die that are very large, people are talking about using a thin-out wafer level package and that means that you basically take this die and you do a reconstituted wafer and then you put some material on it to fan-out the I/O, so you can have like a really high I/O like 400 I/O or so and still keep it in a wafer level package, a low profile because a lot of people want to do that. It’s got some of the big companies out there, the handset makers like Apple demand that these things be less than 1 point a millimeter pitch. And the interesting thing is some of these companies can actually go to a thinner wafer level package in a thin-out version and it actually will improve some of the reliability for the kind of interested.
So there is a lot of people that are doing this kind of thing, ADL Engineering, Amkor, ASE, Deca, Freescale, FCI/Fujikura, J-Devices in Japan, NANIUM, Nepes, SPIL, STATS ChipPAC and so, some times I put up a slide and see a new name here. Because everything I turnaround there is somebody else in there. But the biggest technology in this area is the one that we’ve developed by Infineon that was why ASE, STATS ChipPAC and NANIUM, is that ChipPAC and NANIUM has the big volume in now.
Now if you look at thin because ma’am, I’m telling you thin is NAND where we continue to see people do things like a flip-chip that would give you a very low profile package, if you put it on a really thin substrate or a wafer level package as you can see down here would give you a virtually the same size of the die and a very extremely thin package, but you’ve also heard people talking about going to something called a 3D IC with a through-silicon via.
Now I want to just stop for a second and say, when I talk about 3D IC with the through-silicon via, this type of 3D, I’m talking about is where you stack chips on top of each other and you use the through-silicon vias to communicate through those chips. Now this is not like the FinFET and things that we are talking about within a die where you are talking about stacking things inside a die. I’m talking about stacking die on top of each other, and that’s a little tricky thing, but the drivers for that remain the same, because people can do first of all, you’ve heard people talk about the high cost of lithography for chips and so that’s really a driver to come up with something different.
Severe interconnect delays, bottleneck for high bandwidth applications, device latency issues, so if you’d have put things together and stack them in die, rather them putting them side by side, we get some advantages; power management delivery distributions and it is ultimately the smaller thinnest package. So if you look at what we are doing in some of the phones, where I told you we had a package stacked on top of a package and that’s a form of a 3D packaging.
If we go down here, and we were just stacked just a die on top of the die inside the package, that would give us a much thinner solution, but the problem is that every time I talk to one of these companies with one of these roadmap, they shipped it out another year, so because it’s not as easy as it look in a PowerPoint presentation.
So what we are seeing that we believe that we’ll go into production with this 3D type stacking with the through-silicon via, it’s probably a lot of our memories. There is a lot of work on flash memory, R&D at like IM Flash, Samsung, Toshiba and others. The catch is it’s got to be pretty cheap for flash memory. So any alternative that’s a little bit cheaper, they might go with that.
But the DRAM stuff on the performance, we’ve got Micron which purchase Elpida, SK Hynix and Samsung, non-U.S. playing in there for a little bit, it has run as the company that has a new architectural memories that is actually shipping some of those fact on in production today, but in very small volumes with very specific applications.
The Micron, the Cube agreement that has been announced with IBM and Intel and others is our engineering sample or promise this year, we actually hear that there will be engineering samples and we will probably have some high volume manufacturing in 2014.
So we really won’t start this stuff. The first thing I think we are going to see is the DRAM and it’s probably going to be next year before we get into really volumes with that and it’s mostly going to be memory, because with memory you are stacking the same type of die. If you try to stack memory and logic together, you are going to get some hot spots on the logic and they are going to come across your memory pass the step that the memory guys want you to operate that thing.
So it’s causing some thermal issues and we haven’t found any thermal solutions for that. So this limitations to what you can do with this, so for that reason, if this stuff keep shipping out and people look at other alternatives, or what they should be doing to come up with a ways to achieve some of the advantages, but yet, not being able to stack it in a 3D with TSV.
So one of the things that people have done is this interposer, which is kind of like a little substrate made out of silicon typically and people would put some devices on that and we talked a little bit about some of those companies that are being doing that. I think we’ve talked about Xilinx, who has put basically taken a field-programmable gate array and partitioned it in a design in a new architecture and where they put little slices on that piece of silicon, and then they use a through-silicon via to communicate between the silicon with the redistribution lines with metal layers connecting chip and then come down to with the through-silicon via that’s only in the interposer not between the chip.
And so basically they’ve got about four products shipping with this not really super high-volume, but it is a really high performance application and you can buy one of those for about $17,000 for FPGA in this configuration. So basically they’ve also done some things where they put different types of chips together fabricated on different nanometer nodes, so that something, it’s a small volume, but it really does help to develop our infrastructure. There is a lot of people in the graphic area; NVIDIA, AMD that have talked about using a silicon interposer to put maybe the processor next to a memory, but it would be like a memory stack let say two to four memory in that.
And so the memory stack has to available for those guys to do it, and they also want these substrates, if they are going to amounted on to be a little cheaper to. We’ve also seeing people talk about the high-end ASIC applications that would go into a network system. Also there is some advantages if you put this silicon interposer if you use it instead of just a regular package that would normally been used when you have the Ultra locate dielectric on the silicon it’s a better matched – mismatch.
And then we’d the conversions the people have talked about tablets, but the tablets that have to be pretty cheap to get to that. So we put a fairly aggressive forecast together to look at where we see silicon interposers. And you know we don’t really have a whole lot happening right now. We’ve got some military applications and stuff like that, but your volume applications for like networking, graphics, servers and stuff, high performance things.
We’ve got some Xilinx stuff going on right now it’s just not high volumes. So we don’t see this getting into higher volume until the stack memory are available for those people to use it with a memory stack. And so around the 2014 timeframe if all goes as plan.
Now another type of package that people can use as an alternative in the mobile space because typically what people would really like to do, is that they would like to take a logic device and a memory device in the mobile space and they would put them together, it give you something really thin, something really high performance, but the problem is they’ve got a yield that’s very high. It’s got to be in expensive, we still got some process issues, we got to work on, we got to solve that thermal management issue, so they can’t do it right now.
So it would replace what we call this package on package that has more than 800 million unit shipping last year for the mobile application. But basically, we really still need to test the die before we put them together. And so if you put them together in a package, you test each package and then stack them together and that’s really what people do right now on the smartphones applications and it look like this middle picture here. And it’s pretty thin, but it would be even thinner, if we could just put them together in a very die form, but we really can’t do that right now until we get this stuff had a better yield at a lower price and solve some of the process and thermal issue.
So what we will do if we will do three other things to make that package thinner. The package on package thinner; we’ll either continue with the flip chip, with a very thin die and a substrate, a thin substrate, we’ll embed the die in the substrate or we’ll do some kind of fan-out wafer level package for the bottom package and put the memory package on top of that.
So one of those things we’ll be doing and different companies are adopting different strategies. So you’ll see one manufacturer with one package type, because none of these guys can really get to what they really want to do is just put the bare memory and bare logic together.
So these are the alternative we’re going to see and regardless of which one you use, so either going to have a bump, a big copper or some form of the technology that Ultratech makes. So the catch is that what ever package technology people hit for this market they have to make these realistic brand. Every time these companies come out with new mobile phones, and this just happens to be the Apple mobile phone introduction. So ramp is steeper and steeper, so that means the companies that want to use that technology whatever it is whether it’s flip chip in on the package, whether it is embedded die, whether it’s a fan-out wafer level package. They want to have multiple suppliers that have the capabilities doing that simply. Really quickly to meet that ramp.
Now this ramp is driving people absolutely crazy in our industry. It’s also requiring the people to make a lot more investment in capacity to be ready for those big ramps. Because you could have people camping out and trying to buy your phone and they could only buy $9 million of it, because that’s all you have. If you’ve had a 11 million, they might have been able to buy more of those. So that’s why these ramps are crazy and it’s really having an impact on what’s going on in the investment, everything in our industry.
So it’s kind of an interesting era that we leave in all driven by these little mobile thin devices. So that’s what I’d like to say to you that I think we’re still being driven by all these thin stuff even though we don’t need it or to make it work better, it’s just the passion thing that’s driving it. And we’re going to continue to see a lot of flip chip packages. We are going to continue to see the copper pillar migration. We are going to continue with wafer level packages, mostly in the conventional wafer level package, maybe some thin out applications. And eventually we will get to this 3D IC with a through-silicon via that you heard people talking about.
But until we get there people are going to come out with new versions of packages and also silicon interposer. Thanks
Good afternoon, I’m Manish Ranjan. I’ll talk about our lithography business, if I can get the slide to move. That’s the danger of presenting, what if the battery runs out unless I’m doing something really, really wrong over here. Even the page down doesn’t seem to work. Now it works. Okay, so I will talk about our lithography business, I’ll first talk about the high brightness LED section and then talk about getting down to packaging business.
For both of these presentations I’ll first discuss the macro market momentum, then the segment growth drivers followed by technology trends that we’re seeing in our business and lastly give you an update with respect to our competitors.
This is a macro level chart that talks about growth of energy, essentially there is a strong correlation between global GDP growth and energy growth. Is the global GDP growth that’s around let’s say 3% year-over-year, we’ll see about 56% increase in energy consumption by 2040. We will also see a significant increase in lustering and as we know lighting is about 20% of the overall electricity consumptions. We believe high brightness LEDs could play a very important role in overall energy cost reduction. To give you an example by 2025 LEDs could alone reduce the cost by 62% just in the United States resulting in about $260 billion in energy cost savings, while eliminating nearly 250 million tons of CO2 emission. Needless to say the technology will become more critical and especially as the cost come down then we’ll see more strong adoption in the Solid-State Lighting market segment.
This slide talks about the capacity increase that we have seen in the last several years. To put it in perspective in 2001, they were about 36 LED fabs, last year there were 166. The last few years we have seen a lot of growth driven by China market segment. China in 2010 had about 100,000 wafers per month 4-inch-equivalent capacity. Last year they had 660,000. In the last few quarters, we’ve seen the market now stabilized. The Chinese subsidies are now over.
So a lot of companies are driving towards the plant modernization, when they are focusing on yield improvements. They are taking a look at cost reductions such as wafer size increase and those initiatives will drive the adoption for our equipment. Asia in generally, nearly half of this business; China is 24%; Taiwan is about 21%.
This slide talks about the adoption of our sapphire technology. In the last few years, we have shipped nearly 50 equipment in this market and we begin with patterned sapphire substrates. Patterned sapphire substrates are utilized for increasing the light extraction efficiency and our first initial step in the segment was to replace contact proximity aligners. Over the last few years or several quarters, we have now penetrated metal pad layer, methyl layer, epi-layer, current blocking layer, contactivation layer. Some of the leading high-brightness LED manufacturers are using our equipment for all these five or six or eight layers depending on their process step.
In addition to sapphire we are also seeing some of our customers drive towards larger wafer sizes, six-inch or eight-inch with GaN-on-silicon technology, which is a disruptive technology. We have shipped multiple equipment into this market segment and for those of you that are familiar with GaN-on-silicon; it has a unique voltage signature, essentially it remains flat for most of the wafer and then it goes up towards the edges of the wafers. We have extensive experience in what wafer handling, unique substrate handling, in our other adjacent markets and we have leveraged that technology in the high-brightness LED space as well.
This slide talks about comparison of economic value overall cost ownership for PSS application. Over here the competition is used Nikon equipment which sells for about half to one third of our equipment and initial system price is the only advantage that they have. But when you take a look at overall cost of ownership or the total cost of ownership it’s nearly 2X for a used equipment compared to ours. And factors that go into that cost of ownership equation are rework rate, for instance on a used Nikon because they were never designed for this application, you could see between 5 to 10x the rework rate compared to our equipment.
We have a much smaller process window. The throughput on used equipment is about to one third of our equipment never mind the cost of maintaining that used equipment. That gets to my summary slide, long-term we continue to see opportunities in the high-bright LED market segment, our equipment sapphire 100 has been well accepted throughout the industry.
This market LED market is driven partly by technology, but mainly by cost and as such we are focused on different ways of reducing costs to accelerate the conversion to sapphire technology.
The next presentation, I’ll talk about the advanced packaging and market update and it’s follow the very similar outline, I’ll begin by talking about the macro market momentum key factors that are driving our business. There are many versions of this slide, but this particular one talks about the ratio of PCs to premium phones and tablets. In 2012, if we take a look at unit shipments, it’s two-to-one by 2017 it could five or six to one talking about the cannibalization rate. That’s pretty important for our exams packing business tool, because flip chip for our segment advanced packing segment historically was driven by computing applications. We bumped all these micro processors, which were single layer application, now we are moving from that to mobile applications, which are more lithography expensive and I’ll discuss that in the next few slides.
This slides talks about the advanced technology wafers as a growth driver for Flip Clip segment. Around 65 nanometer technology node we started to seeing a lot of larger companies a push for flip chip and we expected that 65% was about 25% to 30% of logic chip requiring bumping. At 28 that numbers jumps to nearly 70% and sub-28 we believe it would be 80% or close to a 100%.
And what’s also important is because wafer bumping is one of the final process steps. So rest is fairly important to our customers, you want to use equipment that has been production proven because by the time the wafer gets to the bumping stages toward tens of thousands of dollars either leading edge wafers. And any variable equipment of process that could introduce risk becomes a significant factor for many of our customers. The point I was making as we have over a decade of experience in the advanced packing segment and therefore the preferred vendor of choice at all these leading edge IDMs and founders.
Jane earlier talked about wafer-level package as a growth driver for the industry, and this slide attempt to show something very similar in over the last few generations of iPhone, I didn’t for down iPhone 1, but between iPhone 1 to 5s you have nearly 50% reduction in area. iPhone 1 had zero wafer-level packages, iPhone 5s has 18 wafer-level packages. And it’s more than passion, it’s also integration of all this technology. When you are integrating so many features in a very thin device, then you need advanced packaging capability, and wafer-level packing to a certain extent becomes an enabler.
This slide talks about wafer-level package growth in 200 millimeter wafers over the next several years. And on this particular slide I have a wafer-level package, to put it in perspective, this is a penny invested 2/2 millimeter wafer-level package. That does all of your power management function.
And it’s becoming somewhat important and therefore we see company’s leading edge analog company such as TI’s, but over a $1 billion or so in Philippines to bring a lot of the capability in house. Earlier this year we also made an announcement to where Ultratech was awarded preferred supplier award from TI’s and with those important of in that announcement is collected 12 vendors out of a less than 12,000 vendors that TI have.
This slide takes a look at different 3D packaging technologies, the market growth on the Y access and timing on the X access. Standout wafer level package over the last several years, we have seen some capacity addition for fan-out wafer level packing. It has not been a significant growth rate moving forward some companies – some limited number of companies are considering fan-out wafer level package, but we don’t believe the growth rate would be very high.
If we take a look at overall 3D packaging solutions in memory modules good plan important drill. Silicon interposer, today the cost is fairly high and once the cost comes down with the open architecture or open collaborations team that where these foundries are driving for OSAT. This could be a growth driver and mixed device integration is probably at least to three years to five years out if not more because of thermal management consideration, supply chains considerations and overall yield considerations.
In general, as we move towards 3D packaging, it gets a lot more lithography expenses, from flip ship, which will single layer to silicon interposer; it could be six layers to nine layers of lithography.
The last growth driver, I want to talk about is the OSAT market segment. In 2012, this was about $25 billion in revenue. The last several years of growth in this OSAT business was driven by copper wire bonding. We believe the next several years would be driven by advanced packaging technologies and bumping will certainly play a very important role of it. And overall, we are seeing somewhat of a structural shift in the Advanced Packaging segment.
Our business 10 years to ago, used to be driven a lot by IDMs and then it moved from IDM to foundries, and today as it gets more cost competitive OSATs will play a very, very important role. About two-thirds 60% to 65% of our business in the advanced packaging units it comes from the OSAT segment.
This slide discusses the competitive advantage that we have in this market. Advanced packaging is very unique and over the last 15 years that we have been in this business, but we have developed a very large number of market specific technology options for both enabling next generation of technology such as front-to-back alignment or to reduce the overall cost of ownership.
In the last decade, we have also competed against 10 plus different competitors. We have competed against Nikon, we have completed against ASML and most of those companies have – most of those competitors have exited the Advanced Packaging Lithography business.
So we take a look at our market share as a function of installed base for all different types of sapphires out there, we have about 92% market share, and that the putting cost associated with large installed base becomes a very key factors that along with the risk of transferring to a newer competitor, newer technology becomes prohibitive for many OSAT and foundry customers as well.
That brings us to my last slide. We are fairly excited about participating in the Advanced Packaging business. Advanced Packaging has moved from a costs function to a solutions function. We believe Ultratech delivers the technology leadership, operational flexibility and the highest economic value for this market segment. Thank you.
Arthur W. Zafiropoulo
Well, I did it, you know I started 15 minutes late and these guys won the race. So it’s really great so let’s open it up for some questions you may want to ask and we’ll have the speakers are l try to answer. One of you can start. Chuck?
Arthur W. Zafiropoulo
I think pricing pressure is not just in packaging, I think pricing pressure is across the board in LED, in millisecond anneals; I don’t think that you meet any one area. As I guided earlier, in my presentation when I looked at the depreciation cost in the equipment that is the major factor. So I think every single company in our industry no matter where they are in test, in packaging and front-end will be under the same pressure, no matter who they are. Yes.
Arthur W. Zafiropoulo
Well, what you ask the question on ALD side and I would have military on the market side. Do you have microphones there?
Arthur W. Zafiropoulo
Yes, so when we should do that, because this is webcast. So could do you that one more time?
Yes. Sure. In terms of the ALD business, it appears that you are looking at the non-semi side of the industry. Why not user ALD for the semiconductor market go into imagine ASN. And then in terms of metrology, those are realistic number of units to expect for metrology in 2014?
Arthur W. Zafiropoulo
On the ALD side, I have no interest in competing with the material. So we have a strategy, but based on outside and so we look for areas like we done so far with laser technology, with flip chip technology, with inspection technology but we bring some marketplace that nobody else has and so we may enter spaces or applications in the ALD space relative to the semiconductors, but we are not going to go directly after any one else here right now. We are going invent new technologies and maybe they are will be there, maybe they won’t, but at this time, we are looking to introduce the ALD products to universities and research lab.
A few years ago, a pretty important guy in Silicon Valley, Steve Jobs, had a mission and if you are remember going back many years ago, he focused on markets, marketing people and schools. And so he had a great roadmap for his PCs that matched and he focused on those two areas and he want to implant the technology with young people and so really I think that as the people in this industry spend less and less in R&D, we have to do our part and add something into the research community. So what we have decided to do at this company is to promote R&D applications with ALD, a terrific technology, very promising, huge technology. I think bigger than PVD going forward in years to come. So we have to start with some basics and not to jump on front.
So I think to go into the universities and to the research laboratories to offer them a flexible and expensive tool for promoting Ultratech also and we’ll go from there. We have ideas that are much bigger in a laboratory or even some semiconductor applications that we work on today. So hopefully they will come to fruition in the years to come and these are really big ideas. These are not copying some else. So we are thinking out of the box in our technology and again it fits in our nano technology roadmap and as I mentioned earlier, one area, I am not suggesting with participating right now. I love the medical field. I mean the medical field has one has great promise and I am not suggesting for military I am working heavily in that, but some day I will.
And the second question in the market, the inspection [indiscernible] did you have question, okay.
Okay. Hello. So in terms of the inspection market, we are shipping like a handful of systems this year a few are revenue, a few are on a expanded evaluation and we have– you are working with customers over the next few quarters in developing the technology and we have around nine to 10 systems next year, which are mainly the second half coming in after the [indiscernible].
Arthur W. Zafiropoulo
Now I should share with you that I have really great growth in this technology. We have been at this now for about seven years and we acquired a company in Silicon Valley that own this technology invented by professors at Caltech and that’s where they came from, I can tell you that, its great technology, and that’s why we bought, and we have several coming and stayed with us, one of the founders of the company and this has great promise and initially what focused on the laser technology for stress, and as we said before for years now that stress is very important in yields.
And we keep say that and people don’t believe that’s true, so a little bit early at all these things we talked about, we talked about the costs that was going to happen in Q1 and it happened. And people said it centrical, that we said no. And we are seeing now some of these things we think about and we talked about and we know about, and this technology is going to be very big, and because it’s certainly very important anneal, and being low cost, low data point, so I think that this is just beginning of another part of Ultratech, if you haven’t seen before and don’t be fool, the laser technology, is still the biggest market and right behind there in growth will be I believe inspection.
And packaging again we are 13% of the world industry in packaging versus wire bonding and we expect that to grow from 13% to well over 50% in next years to come. So all these technologies that we bring to the marketplace have tremendous potential, but each one have this different market sizes. So big market size we are dealing with is lasers. We’ve talked about 1 to 2 billion in logic alone. We talked about 300 million, 400 million inspection. We talked about 200 million and 300 million in advanced packaging.
We talked about 100 million per year maybe if we can overcome this cost issue in the LED space. So we are looking at each of these areas as tremendous growth potential. So next question please. Well, I want to get you out of here, we got four more minutes. I have not you guys can early. Yes.
I was wondering if you could remind us how the total opportunities for the laser grow when you go to $0.14, $0.15 from 28 in your opinion, is it seem like some customers are using fewer millisecond anneals that some are using more.
Arthur W. Zafiropoulo
Yes, we got to be very careful, I think that really some of the analysts in this room and others should be really do some real research on what performance gains are generated by hybrid FinFETs versus FinFET, and so that if you take a hybrid device that uses two layers, millisecond anneal and you’re going to a full hybrid four or five layers then you have to see what the benefits are, and I think it’s just on them to share with you what those gains as opposed to – you ask to me that question as an equipment manufacturer, but I can tell you, that the gains are enormous that the industry will shift to more and more layers on millisecond anneal, and we believe that will be primarily based on laser technology from the comments made earlier by the presenters.
So we are very comfortable where we are and the question isn’t when we are going to get bigger, the question, is that how big we are going to become. So I think it’s just a matter time and as you will see hopefully sooner than later this is going to be a very big company and one that you would be proud of. Josh? I want to go to Josh, next.
Just sort of in the same line of thought, you talked a little bit or I think that Jeff had talked about, LSA revenue by node, probably not in a position to give guidance for us this year or for next year, but can you maybe help us think directionally as to how big that business might be in 2014, since its sounds like you have visibility as to where the tools are going?.
Arthur W. Zafiropoulo
Yes, that’s a hard question. We get guidance and I will share with you. I’ve had a couple of analysts come back to me and asked me why. Previous guidance next year of 20% growth of this year and some of you may think it’s kind of conservative but, we don’t have a lot of visibility, but we have at least 20% of visibility. And so we feel at least for starting point. And we want to make sure that you guys can take your own numbers. If really give a number to start with and you have your own numbers to pick up, we’re going to skewed to that, so we pick those numbers. So let me give you for instance, here’s is one company and I won’t tell who they are. It’s planning a 40 nanometer fab of over 100,000 wafer starts per month.
Remember what I said that both Qualcomm and Apple in three, four years each will be over 2 million wafer starts per year, but just put that in perspective. And they are going to be doing a 100,000 wafer starts and this is a company we believe will use about four layers of LSAs. They may require 50 to 60 systems that’s $400 million for that one fab. I am not suggesting that next year is going to be bad year, because it doesn’t take one year to fill a whole fab, but that’s just one example of one fab of what they could use in LSA based on what we know today.
With respect to this technology – technology hurdles facing in industry. Are you quite confident that we are going to see a shift downwards to I think people were planning 40 million, plus they plan with packaging improvement et cetera, sometimes those plans kind of shift out, if we cannot, if there is no visible way to really rack down on price per gate.
Arthur W. Zafiropoulo
That’s great. I had only two things that I could guarantee will happen in the life; I am going to add a third one. I had does in practice in 14 nanometer. So yes, the answer is absolutely it’s going to happen. If that doesn’t happen the entire food chain will collapse; Apple, Qualcomm, the entire food chain in the tablet mobile market will collapse. Unless I can show a generation of improvement in devices to see that market, we are going to be in deep trouble, so you can sell them short. We believe that’s true.
With that I want to thank you very much for coming. And I hope you enjoyed today. And look forward to see you next week. Thank you.
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