I cite a quotation from Intel TV Flop Is Huge For Investors by Rizzi Capital "I am sure that given Intel's massive R&D budget, coupled with its world leading engineering talent, the OnCue device and television service would have been a quality product. Erik Huggers, a former executive with the British Broadcasting Corporation led the 300 employee strong team, which developed the device and then negotiated terms of the media distribution agreement with major networks. By most accounts, the team did excellent work. The device prototype was tested by Intel employees and considered to be far superior to other products on the market offered by cable and satellite companies. Although the full rollout and launch of the product would have been expensive, it stood a good chance of being successful."
But Brian Krzanich, Intel (INTC) CEO, saw this program as a distraction - a new product in a new market. So you can conclude that Krzanich believes Intel needs to capture a larger share of the mobile and tablet market and that it also needs to produce something that will fill its new FABs and have a higher chance of success at an equal or larger volume of business and profit as compared to OnCue. And that appears to be what they are proposing to do with the opening of the Foundry to all the customers who can pay for that service.
Seems like they can't lose in the Foundry business. Or can they?
What do they need to support the volume of customers they have invited to participate?
Unlimited volume capability (no problem).
Competitive pricing (there isn't any real competition).
Training and support (uh, uh, uh, ……..)
So what's the problem? Well the problem is that Intel doesn't have the support that many customers are going to require. And it doesn't have the infrastructure to supply that support.
Customer: "Show me an Op -Amp that has 60 DB of open loop gain and a 1 MHz Gain Bandwidth Product."
Intel: "We don't have any of those."
Customer: "Show me an 8 bit DAC that has ½ LSB linearity and runs at 300 MBPS."
Intel: "We don't have any of those."
Customer: "Then can you teach me how to design these elements?"
Intel: "Teach? We don't teach, we make chips."
And so on! Why is this the way that it is? It's because Intel is a digital UI company, and the world is analog! Intel has concentrated on designing IP for digital applications and scaling that IP to more advanced processes. This sort of works with digital IP and planar processes. But when the world moved to sub 100 nm, and particularly moved to 22 nm FinFETs, the whole idea of scaling came into question - and the idea of scaling analog IP became a sick joke.
Arguably, the current crop of analog IP is roughly the same size as (or larger than) it was at 90 nm. If you don't believe me, ask around. This problem is largely related to the fact that analog design rests on the use of matched transistors. As feature sizes get smaller, Intel's ability (and everyone else's ability) to create matched transistors becomes compromised. A first order solution to this problem is to put many small transistors in series and/or in parallel with each other - thus synthesizing a much larger transistor that behaves like it was made in an older technology node (funny business this is!). On top of this, it's beneficial to put these transistors in specific places in the layout to get them to behave as well matched as possible. And it's also beneficial to make all of the transistors reside in locations so that the environment in their vicinities is identical. When you finish doing all this, you are still going to be faced with the problem of how to get 1.5 volt (or 2.5 volt, or 3.3 volt) signals using 1.0 volt transistors.
With so many balls in the air, there is not much you can do - unless you come up with some new analog circuit designs - something I found many Intel managers to be averse to making investments in.
Why? Well, microprocessors are 99.8% digital.
Question: Who cares if 0.2% of the layout is 10 times larger than it could be if Intel invested $2 million in a better opamp?
Answer: Anyone who needs a high performance opamp that can't be built by using an existing design. And - anyone who needs an 8 bit DAC that can't be built using an existing design. And, etc…
And the problem is, that many of the people who will be concerned about this are potential Intel Foundry customers.
More difficulties arise because of the differences between the parasitics in the older planar processes as compared to the newer planar and FinFET processes. For one thing, the RC product of the fine line interconnects is much higher, per unit length, in the newer processes. This happens because most of the capacitance in these lines is edge capacitance while the resistance is inversely proportional to width. So fine lines have almost as much capacitance as wider lines but have more resistance than wider lines. Since the RC product helps determine rise time and time delay (caused by diffusion) in long interconnects the buffered sections of lines must be much shorter to work as well as older processes. So these long interconnects require a lot of buffers.
FinFETs have much higher capacitance than planar FETs; they also have much higher transconductance than comparable planar FETs. So they have faster rise times and less time delay - but - they can't support long interconnects without buffers.
Because the transconductance of the FinFETs is very high, small transistors can draw a lot of current from the power supply to support high clock speeds and/or analog functionality. That's both good and bad; good that they can support high performance and analog functions, bad that the high currents in the small transistors leads to electromigration that can result in shorter functional lifetime.
All of the above issues require close attention and design expertise.
So what's the problem? The customers can design those blocks, or at worst, they can hire someone to do so. Right? Well, good luck at finding an Intel digital designer who wants to do this for you. And fantastic luck at finding an Intel analog designer who can do this for you. Did I say "luck," well I really meant that you would have to offer obscene benefits to get the people you needed - and there's the rub - high performance and reduced silicon costs if you can find designers and afford to pay them.
Intel is not going to be running many fire sales. While it's true they have announced a policy of subsidizing customers who are replacing ARMH chips with Intel chips, the subsidy will likely depend on sales volume. High volume customers may get enough money to actually move an ARM design to Intel FinFETs without breaking the bank. Smaller customers, beware! Probably good for Intel and bad for the smaller customers - also bad for ARM (because they will wind up with a higher percentage of small customers).
And one more thing: Intel doesn't want any of its Foundry customers to give a copy of a netlist for a Silvermont architecture SOC to anyone who will try to port it to TSMC (TSM), Samsung (OTC:SSNLF), GlobalFoundries (privately held), or anyone else. So they will have to put some sort of security in place that makes such a netlist (and the layout, and anything else that can be used by a thief) impossible to access and/or copy.
So, as we are in the real world, nothing is simple. You have to have been there to really know the full story, and what I have given you is basically Cliff Notes - not the book. Think about how tough it's going to be to generate the analog and mixed signal libraries the Foundry customers will want, and to provide the security required without compromising what the customer needs to do to design a chip. It can be done, but it needs a plan to do it.
And, by the way, I'm actually one of the guys who figured out a way to build 1.5 volt circuits with 1.0 volt FinFETs. My design exists in an earlier planar Intel process. Couldn't get them to buy in - even though there was a working example that was being sold. Oh well, that's the way it goes!