When Intel (NASDAQ:INTC) introduced the 45 nm CMOS process for Nehalem, they also introduced a series of process changes that had the effect of reducing gate leakage and improving gate control, increasing p-channel mobility, and improving overall process yields.
Intel introduced 3D FETs because further scaling of planar FETs appeared to be non-productive. The scaled FETs would be smaller, but their leakage current would be a larger percentage of their maximum active current - resulting in more leakage power going forward. Leakage power was the primary contributor to power dissipated in planar CMOS in the 32 nm generation.
Those changes appear to have been, or are being adopted by all the major suppliers of CMOS integrated circuits. That includes TSMC (NYSE:TSM), GlobalFoundries, IBM (NYSE:IBM), and Samsung (OTC:SSNLF).
As a slight divergence, I want to observe that whenever I talk or write about any of these changes, I am accosted by a coterie of naysayers who simultaneously deprecate the importance of these advances and underestimate the time required for their favorite Intel competitor to duplicate Intel's improvement! I can't rationalize the fact that they are coming at me from so many contradictory directions at the same time.
I guess that they are fueled by the predictions of their favorite Intel competitor. Here is a copy of the prediction for GlobalFoundries, courtesy of Mike Noonen, Executive VP, Global Sales, Marketing, Quality, and Design in February 2013:
Global Foundries lays out their FinFET plans
Common Platform 2013: Welcome to the new 14XM and 10XM processes
Feb 8, 2013 by Charlie Demerjian
As you can clearly see, he predicted the availability of 20LPM to have happened almost a year ago (hasn't happened yet) and 14XM 3 months ago (not expected until end of 2015 - if then) and 10XM in the 4th quarter of 2015. Intel may make that date - but GloFo??? Give me a break! If you actually read the reportage that accompanied the release of this chart, you find out that what GloFo actually planned to do was to use the existing 20 nm back end and the same software as used for 20 nm - a long distance from a real 14 nm process, and they didn't even come close to doing any of these. Instead they grabbed a life ring from Samsung, and they are now way out there in terms of real production - probably the end of 2015 to the middle of 2016. And 10 nm was just a shot in the dark, and their actual target was test runs at the end of 2015, not production as is implied by the slide - they won't even be able to smell 10 nm in 2015. Bet on 2017 to 2018. So much for GlobalFoundries.
How about TSMC?
This one should make you laugh! It shows what TSMC was telling their customers at the beginning of 2013. CLN20SOC at the end of 2013? It actually may happen sometime soon! And CLN16FF in the 4th quarter of 2014? It's actually tagged to the availability of 20SOC, so if I read the chart correctly, it's going to be about a year later! As for CLN10, it's really anybody's guess. TSMC has a dotted line around it - indicating that they are not so sure about what they are talking about.
What about Intel? How pure are they?
On May 17, 2011, Intel announced a roadmap for 2014 that includes 14 nm transistors for their Xeon, Core, and Atom product lines.
In September 2013, Intel demonstrated an Ultrabook laptop that uses a 14 nm Broadwell CPU and Intel CEO Brian Krzanich said "[CPU] will be shipping by the end of this year." However, shipment had been delayed further until Q4 2014.
The excerpt below: Quoted from dailytech.com:
"First 14 nm chip will likely not be ready until the holiday shopping season, after defect issues.
Before 2013, Intel had seen several years of aggressive updates to the Core i-Series. Each spring would bring fresh announcements of "ticks" (die shrinks) or "tocks" (architecture refreshes), which would alternate on a yearly basis. By the summer months, these chips would have found their way into high-end laptop models.
I. The Slippage
But eyed more carefully, signs of slippage to Intel's breakneck pace have been showing. Sandy Bridge, the second generation of Core i-Series processor launched in Jan. 2011 (Q1 2011) and began shipping almost immediately. Ivy Bridge -- the third generation Core i-Series chips -- were released a bit later, right at the start of Q2 2012 in April 2012. As the release -- a die shrink to 22 nanometers -- brought the tricky-to-manufacture 3D FinFET technology to the table, most wrote off this slippage as natural.
Likewise last year's Haswell, Intel's 22 nm architecture refresh, slid back a few more months to June 2013. Some did notice this time, with rumors mounting that the die shrink to 14 nm -- Broadwell -- might be delayed until 2015. It turned out the reports were somewhat true -- Intel was suffering much higher defect rates than previously expected -- but Intel insisted that Broadwell chips would be delayed only a quarter, to Q1 2014.
But Q1 2014 (Jan. to Mar.) came and went and Broadwell still was a no-show in terms of shipments to OEMs. In an April 2014 earnings call, CEO Brian Krzanich insisted that the wait was almost over, saying that the chips would ship sometime in H2 2014. Most hoped this might mean Q3 2014, in time for the August-September back to school shopping season.
However, while attending the Maker Faire in San Mateo, Calif. this past Saturday Mr. Krzanich delivered some disappointing news to Reuters. His comment hints to investors and customers not to get their hopes up of seeing Broadwell product shipping in time for that key sales season.
"I can guarantee for holiday, and not at the last second of holiday. Back to school - that's a tight one. Back to school you have to really have it on-shelf in July, August. That's going to be tough."
If the Nov. - Dec. shipping window (perhaps with a September soft launch at the Intel Developer Forum) proves accurate, Intel will have lost nearly a full year in terms of slippage over the past four launch cycles, starting with Sandy Bridge.
Broadwell should be available in time for the holidays.
This slippage originates from the high defect rates that every chip fab company encounters when moving to smaller nodes. Intel typically tapes out test runs of chips and then must make the difficult decision of what will cost more -- the chips scrapped due to defects for the present process, or the cost of waiting and pushing back the refresh. No matter what Intel chooses a fair amount of chips will be lost to design flaws, the trick is minimizing that number."
So Intel messed up too. But it appears to me that they told us what was happening at each stage and tried to make reasonable predictions based upon what they knew at the time.
It is important for you, as potential investors in these companies, to understand this history, especially the trustworthiness of predictions, and to be aware of future potential changes that are in the wind and when they will likely occur.
In 2010 the results of an Intel research project were published in the IEEE Journal Of Solid State Devices. Briefly, this paper described a project to develop the architecture, circuitry, and optical components required to transmit up to 40 Gbits/second over an optical link between a computer and an external transmitter/receiver. Briefly, real experiments were performed and data was obtained indicating that high quality links could be built using a 16 nm process, requiring a power dissipation of 1 pico-joule per bit. It is of note that the paper described work that was done earlier and resulted in patent applications that were filed in 2002 and 2004 - and granted in 2003, 2004, and 2006. The subject patent numbers are 6,512,861, 6,754,407, and 7,049,704. Two of these patents bear the same title "Flip-Chip Package Integrating Optical and Electronic Devices and Coupling to a Waveguide on a Board."
Now comes the other shoe! Patent numbers and titles are shown below:
8,532,449 Wafer integrated optical sub-modules/September 10, 2013
8,412,052 Surface mount (SMT) connector for VCSEL and photodiode arrays/April 2, 2013
8,383,949 Method to form lateral pad on edge of wafer/February 26, 2013
8,230,589 Method of mounting an optical device/July 31, 2012
This second group of patents were granted much more recently. Get the drift?
The first group was the conception of the invention.
The second group was how to actually build it. Logical reasoning brings me to the conclusion that Intel is in the implementation phase of optical interconnection of high speed signals using the methodologies described in these patents. They would not have applied for this last batch unless they felt they were close to a product release - because patents expire and they want to have maximum useful life for this kind of patent, in particular.
So, what's the implication of these programs and the associated patents?
As CMOS transistors become smaller, they become faster, but they also make it harder to build quality analog circuits - those that have high gain, good matching, high yield, etc. High speed I/Os, which are actually small systems involving various programmable elements (to control gain, offset, impedance, and edge rates - among other factors), become more complicated, expensive, and difficult to extend to the next process node. On the other hand, optical components like phase shifters, interferometers, and lasers can now be more easily built - either in integrated or hybrid form - on chip where they are easier to drive electrically with minimal parasitic capacitance and inductive reactance, which would otherwise degrade the interface between the electrical and optical components. And using optical interconnects virtually eliminates frequency dependent wire losses that would otherwise occur in the connection between the chip and its surroundings. These advantages lead to greater bandwidth and reduced power - just what you need for servers, PCs, and mobile devices.
What else is coming?
2D and 3D multi-chip integration
There are a series of patents that deal with vertically stacked 3D circuits and other techniques for connecting multiple chips within one package. One big reason for doing this is to simplify and speed up the interface between the processor and memory, and greatly improve performance (5X?). A second big reason is power - by reducing the amount of circuitry involved in the memory interface and easing up the drive requirements for the memory (because of the shorter wide bandwidth interconnect) considerable power savings are achieved. These patents are listed in two groups because of the search mechanism used to find them. One group deals largely with connecting I/Os - many through optical means, and the second deals largely with connecting parts inside of one package, either vertically or horizontally. To view any of the following Patents type the Patent number into the link that appears when you click here.
Notice that both groups contain references to optical coupling of chips. This indicates that there is a major Intel program that takes advantage of the disruptive technologies described in these patents. Also notice that this work has been going on for a long time - since the start of this century. And note that the character of the patents has moved from largely architectural to largely implementation, a sure clue that things are coming to a conclusion. It looks to me that we will see the fruits of this program in the next year or two, and this will produce a further advance in technological superiority for Intel.
Further, the techniques being developed will allow Intel products to run faster than their competitors, to occupy less space, to consume less power, and to increase communication rates by a large factor. Looks to me like a multi-dimensional disruptive set of technologies.
One could argue that a significant part of the recent increase in Intel valuation is the result of the perception that FinFETs will allow Intel to increase their mobile market share and also become a strong player in new markets - IoT for one. I agree and I perceive a similar result following the introduction of products bearing the disruptive technologies described here.
Disclosure: The author is long INTC. The author wrote this article themselves, and it expresses their own opinions. The author is not receiving compensation for it (other than from Seeking Alpha). The author has no business relationship with any company whose stock is mentioned in this article.