Lam Research Corporation (NASDAQ:LRCX)
2008 Analyst & Investor Meeting
July 15, 2008 4:00 pm ET
Carol Raeburn - Senior Director of Investor Relations
Martin B. Anstice - Chief Financial Officer, Chief Accounting Officer, Senior Vice President
Richard Gottscho - Group Vice President, General Manager - etch Products
Stephen G. Newberry - President, Chief Executive Officer, Director
[Jackie Fikel] - Vice President of Product and Strategic Marketing
Welcome to our 2008 Analyst and Investor Event. Before getting started I want to remind you that today’s presentation contains forward-looking statements and actual results may differ. The risk factors that could cause results to differ can be found in our most recently filed 10K.
Joining us for today’s event are Martin Anstice, Chief Financial Officer, Jackie Fikel, Vice President of Product and Strategic Marketing, Rick Gottscho, General Manager of etch Businesses, and Steve Newberry, President & Chief Executive Officer, who will conclude our presentation and seek questions from the floor.
Please note this meeting is scheduled to end promptly at 2:30 p.m. We request that you hold your questions until the end of the presentation. As the meeting is being web cast please wait for a microphone before asking a question. Please be reminded that our quarterly conference call is scheduled for Tuesday, July 29, and we’ll answer your questions related to the June quarter at that time.
Now I’ll hand the meeting over to Martin.
Martin B. Anstice
I’m going to spend a little bit of time here talking about some historical perspective very, very quickly and then kind of getting into the headlines of the recent couple of quarters and where we’re headed.
So as many of you appreciate the story for the company in the last several years has been kind of defined around significant market share momentum in the hedge business. We have six consecutive years now of market share gains and obviously that translates into something meaningful in terms of revenues, profits and cash generation for the company, and we believe we ended the 2007 year in the range of 48%, 49% market share in the hedge business.
What goes with that is financial performance, we have now five consecutive calendar years of revenue growth, and I think worthy of comment we pretty much doubled the size of the company in revenue terms in the two years 2005 through 2007. And I think the 2006 and 2007 period was probably one of the most illustrative of the market share gain in the company. We grew revenues in the 2006-2007 transition in a range of 19%, the shipments were in the range of 8% growth, and wafer fab that year was a 2% to 3% growth year. So it really is easy to demonstrate market share when you’re a single product company and of course in that timeframe more or less we were.
Cash generation for the company is very strong. You’ve heard us many times talk about an ambition to deliver 25% of revenues in cash and operations, and in the four years ending 2007 we exceeded that. We had kind of one year slightly above and one year significantly above that, but overall in that four-year period a very positive story for cash performance in the company. And that enabled approximately 20 million shares to be taken out of the share accounts of the company through repurchase in the last couple of years.
For 2008 we’ve had a very, very clear focus on delivering and sustaining financial performance of our hedge business. One of the things I will share with you today is a little bit more disclosure in the company about our investments in non-etch products. I’m going to get quite specific about that focusing on the plasma based products and then also talk about SEZ. But one of the critical headlines that we should make clear is that our hedge performance continues to deliver strong financial performance to the company and that is one of the enablers for the investments in new products.
We have clearly focused continually on asset performance and I think you’re well aware, whether you focus on the receivables performance of the company or look at 50 to 70 days based on outstanding performance or inventory in five to six turns, we set the standard or we’re up there setting the standard with other well-performing capital equipment companies in this business. And that’s a big part of the message for the recent history and also the future.
We are investing in growth organically and inquisitively, and I’ll talk about both specifically in a few moments. And this is the year where we are generating revenues from new products. So about 12 months ago we stood here and said, “It seems like absolutely our expectations for revenues on new products are kind of not going to translate in the 07 year,” and that’s not the message we’re delivering for the 08 year. The message for 08 is, “This is the year we are generating revenues on our new products.”
And we have commented in the first half of this year our integration of SEZ. Our second half focus is, as Rick will speak to in a few moments, building upon defending and further strengthening our application penetrations in the hedge business, accelerating our new products and operations and revenues, and working on clean group financials. And I gave a baseline for that in our recent earnings cal and I’ll be more specific in a few moments.
Not to reconfirm or otherwise but really just as a frame of reference, I wanted the slide that shows the guidance for the June 08 quarter and as Carol already indicated we’re only about 10 days or so from being on the conference call and explaining the financial performance for the company for June. But given that there’s a lot of moving parts, given that there’s an acquisition, and given that there is significant investments in the business, I wanted to spend a moment explaining how to bridge from March to June as a basis to help you from a modeling point of view.
Obviously the revenue expectation for the company for June was down and on the earnings call I actually broke out for you the traditional Lam business, the core Lam business, and the SEZ business. Lam at the midpoint was about 515 so we’re about $100 million down in core Lam business. And as I’ve said for the last couple of years, about a point of gross margin happens for every $50 million. And it’s not quite as precise as that up or down but as a generic kind of modeling basis, that’s not a bad frame of reference. So a couple of points of the margin reduction are simply a function of volume.
We have a mixed concentration, we have an SEZ business, and in the SEZ business we have some accounting challenges but really had a business profit origin. And I didn’t explain that very well in the earnings call but the acceptance-based revenue models for us with the SEZ business is intended to provide the same benefit that we get in our hedge business. And that is we get everybody in the company focused on collection and if we get everybody focused on acceptance and collection, we get cash faster.
And so there’s a business reason for doing it, there’s an accounting byproduct in the acceptance model, but the 12.5% operating income number here and the operating expense expansion between March and June is almost exclusively SEZ based. So the underlying core between March and June for Lam is essentially flat in terms of operating expenses.
I wanted to spend a few moments talking about leverage. We spent a lot of time building our business. Our business model has been in place now for at least five years. In fact many of us were working and planning two years prior to that. So a lot of work over a long period to institutionalize a behavior and a discipline in the company that not only delivers good financial results but gives good performance to the customer. And it’s responsive service levels which are on-time delivery and lead times; we’ve been improving both in the last several years.
It allows us to avoid significant investments in our business in infrastructure. We have in a range of about $70 million to $80 million of capital expenditures in the company. We’re a little less light than we used to be but we’re still very light compared to most of our peers in terms of the CapEx and we have a significant and sustaining variability in our OpEx. Obviously our above-the-line costs, cost of goods sold, are not exclusively variable but they are highly variable.
So now comes a little bit of extra disclosure, I wanted for the first time to give a little bit more perspective on where we spend money in operating expenses and as I just highlighted we’ve got about $145 million of operating expenses in the March quarter. We guided $168 million or so for June. We have variable based compensation that is about a $20 million hit to the company in the March quarter, 15 below the line, and to a large extent that is almost directly correlated with operating income performance. And one of our objectives was to reward the employees for the performance of the company and that includes the all-employee rank and file population as well as the executive team even to the extent of long-term compensation.
We also have investments in the range of $30 million for what I’ll call organic new products, and for us that’s the C3 linear platform, the clean product, the bevel clean platform Coronus, our patent enhancement product Motif, and our 3DIC product Syndion. We invested in the March quarter in the range of $30 million in that business. That’s $15 million and $5 million and $30 million, obviously are a significant component of our operating expenses. They were in the range of one-third of our operating expenses in March and they represented about 8% of the revenues in that quarter. So we’ve clearly been investing in growth organically and acquisitively.
And I wanted to just illustrate the organic side of that investment by focusing on the headcounts of the company. Many of you will be aware that in the last 18 months or so I used September 2006 as a framework. We have increased the headcount from about 2,500 people to 3,000 before SEZ. The good news is that headcount expansion happened exactly where you want it to happen. It happened in the area of technology investments. Our hedge business and our organic new products in plasma and non-plasma benefitted from that investment in technology, in our headquarters and also in our field organizations. We very efficiently added headcount in our field service organizations.
We have obviously built a significant install base. Our 2,300 install base at the end of March is around 5,800 chambers for a significant install base for the company, and that period of expansion allowed us to obviously realize significant return in our install base customer service business. We added about 50 people in our manufacturing organization and as a byproduct of integrating one of our suppliers, one of our critical suppliers in terms of product differentiation Bullen Semiconductor, we added about 220 people to the headcount of the company. So of that list 450 to 500, obviously the key message and as a byproduct of the acquisition we added 850 people at the time of the deal.
So why are we doing this, is perhaps an obvious question and Steve and Jackie both will both talk to some of the specifics. But the foundation for this investment plan record is delivering growth in excess of the pace of growth in the industry. You’ve heard us talk about adjacent market expansion and you’ve heard us talking about targeting to grow significantly faster than the industry. And our job obviously is to do that in the long term and we are as a byproduct of our performance in hedge investing in our products.
So what return are we targeting and when are we targeting return? I’m going to do this in two segments. One is to focus on the organic plasma-based products, so this is the bevel platform, the [inaudible] platform, the 3DIC platform. We are targeting a cash flow positive year in 2009 for all of those products. We’re targeting revenues by 2010 in the range of $250 million with a gross margin of 50%. And the investment product all around those products was defined around realizing operating income positive by the third year of meaningful investments and meaningful investments to me is around $1 million in R&D in a year.
So that three-year cycle began on the day that we had $1 million of R&D invested in a year. And we’re targeting to be around about 30% operating income on those products. The headline year for the plasma-based organic expansion of the company is very efficient. It’s a very highly leveraged growth play for us from our hedge business and obviously the financial numbers reflect that.
Turning more specifically to the SEZ business, as a reminder, the reason for this investment was hopefully very clear to most of you. It is very central to the adjacent market growth strategy that we had defined a number of years ago now and the leverage is defined in any number of ways not least by the fact that 50% of the clean steps in our fab immediately follow an etch process step. So from a knowledge point of view, from a profit sequencing point of view, high leverage and obviously we have made our own commitment to an organic investment in the business by way of our linear platform.
We have described for a number of years now that an acquisition by the company was not a I would say a strong priority but it was something we would consider if it enabled us to accelerate the pace of delivering our strategy and/or get there bigger. So it was faster or bigger. And for sure there’s no doubt that we’re getting there faster as a byproduct of this investment and as we’ll share more specifically in Jackie’s presentation, we’re targeting to get there bigger as a product of the investment.
So this is about technology exchange, it is about leverage, it is about making both products more competitive in the market place and it is about positioning the collective offering of the company to exploit a significant transition on the front-end-of-line clean profits fetched from batch to single wafer. And the risk of minimizing the message from Jackie in a few moments, that’s one of the biggest headlines - significant growth leveraging capabilities from both companies, install base, technology, process, hardware, you can kind of name attributes of complements for a while here.
The integration vision; when we began to communicate with you this transaction, we had an expectation of a $30 billion wafer fab year I think at the beginning of this year and we’re sitting here today around $24 million or so. What goes with that transition is a responsibility by this executive team to accelerate some elements of the integration. So the pricing of the deal and the acquisition integration objectives at the outset were not defined around significant cost reduction. Many of you appreciate that timing is everything. And one of the realities of our linear-based clean business is that we were at the very early stages of building infrastructure particularly in the field to install and support the equipment.
And what the SEZ allowed us to do was to provide an infrastructure to grow into while the change in the economics in the industry has driven us to prioritize some cost reductions. And I will talk very specifically in a moment about what we’ve done in June and what we intend to do prospectively and what the implications of that are going forward, but we have created a single face for the customer defined around our global account structure - that was pretty fundamental in all that we stopped competing with each other - and deliver the right product to the right application for our customers. We have leadership from both companies committed to delivering the strategy that we have articulated to. We’ve implemented a first stage of cost reduction and we’re planning actively here our second.
So our expectations going forward, we anticipate that the previously communicated $0.40 dilution is generally likely. We’ll be in that range which means that to the extent that I’m now going to describe some cost reductions, when I said that in the last earnings call we were anticipating that plan. We obviously have restrictions over what we can communicate relative to the employees’ sensitivity of that plan, but the $0.40 dilution range for the calendar ‘08 year is still in the range of what we’re talking.
Very, very specifically and importantly we are targeting significant operational asset performance improvement in the ‘08 year and our objective is to deliver positive cash and operations from the SEZ business which means driving about $75 million of operational cash performance that would not have existed as a standalone business. That’s focused in the area of payment terms, collections and installational warranty and also some inventory management improvements as well.
We will announce in our upcoming earnings call a restructuring of the SEZ business and some of our own clean business incurring a one-time restructuring charge of $15 million to $20 million. Our expectation is that delivers an annualized $25 million saving taking the break-even point of the combined clean group to about $85 million to $95 million. We are actively planning a second round of synergy type activities focused on back-office and infrastructure and that’ll occur according to our current plan on or around the end of the calendar year.
So in summary, we’re focused on executing clearly to the needs of our customers, extending our position of leadership in hedge, leveraging that expertise across our adjacent markets as we have defined, and continuing to focus on delivering best-in-class financial performance to our shareholders. We do have a flexible business model. We are choosing to take an opportunity to invest in our long-term future and I hope what I’ve just communicated provides a bit more perspective about your own modeling for our financial statements. And we are actively invested today in accelerating our integration of the SEZ acquisition, in large part a byproduct of today’s economics.
With that I’ll pass it to Jackie.
Today I’m going to talk about what is happening in the single wafer clean market and what products Lam has to address this market. As Martin mentioned we believe that the single wafer market is going to outpace the wafer front end equipment market mainly because of the migration from batch to single wafer that’s happening and this is driven primarily by yield. The yield due to issues that a batch processing causes, which I’ll talk about as we go forward, and also yield because there are times where you can insert clean applications into the process slow and increase the overall designs yield for the products.
We believe Lam is uniquely positioned to meet this market and the reason for that is with our combined product portfolio between Lam and the SEZ products that we recently acquired we have spins clean technologies, linear clean technologies, and plasma-based clean technologies. And the combination of these three is more extensive than any other single wafer clean product portfolio around and this will enable us to address the challenges that are coming up in the market. We believe we can leverage the combined knowledge between the companies and also leverage the knowledge from etch to really develop differentiated single wafer clean technologies and solutions to meet the challenges that are going to happen.
As you go down to 45 nanometers and 32 nanometers we start getting into features, high aspect ratio features, and very complex film stacks some of which Rick will talk about in his presentation. From a clean standpoint this makes it very difficult to remove defects, remove particulates without damaging the device and with our technology that we have combining clean we should be able to do that.
And I’ll show you that we’re strategically positioning ourselves this year to have strong growth in 2009 and beyond 2009. If you look at the overall market size on the left-hand side, what this is showing is what we believe is going to be the market size of the totality of the clean market through the years and the orange shows what the single wafer clean market sizing is without scrubbers.
On the right-hand side what you see is the percentage of adoption of the total market of clean to single wafer clean. So right now we’re sitting at about 30% adoption. We expect that that’ll grow to about 47% adoption by 2010. We expect that the single wafer clean market will grow to about $1.2 billion by 2010. And as I mentioned before, this is driven by the adoption of single wafer clean in the front end of the line application for yield and also for the addition of some applications specifically for bevel clean to improve device yield.
Today single wafer clean is already used extensively in back end of line post etch cleans and also in back side and combined back side bevel applications. At 45 nanometers we’ve seen the introduction of the bevel-only clean and so this is where we’re cleaning the edge of the wafer, just the bevel, either removing polymers or removing films to prevent those films from then redepositing inside the wafer and causing defects which would kill the device. And those bevel-only applications can only been done on single wafer. In a batch system the whole front of the wafer would be exposed to chemistries. And what you want in these applications is to only expose the edge of the wafer to chemistry.
In 2010 we expect that a majority of front end applications will also transfer to clean, single wafer clean, at leading edge companies. And if you look at this, what this is showing is where we expect single wafer clean to be at a variety of companies in NAND, DRAM and logic at 2010. If you look here, you see that in DRAM and in logic and foundry some of the leading early adopters have already gone beyond 60% in the number of clean wafer passes that are now at single wafer.
And what this shows is that if the NANDS market or if some of the other companies within the DRAM and the logic space decide to adopt the same strategy, the single wafer clean market could actually accelerate beyond what we’ve already shown so beyond $1.2 billion and beyond 47% overall adoption rate.
Just switching a little bit to look at the evolution of cleans from batch to single wafers. At 65 nanometers as I mentioned earlier the back end of the line post etch and the back side was already running on single wafer technology. At 45 nanometers we see the introduction of the bevel-only processing which is the single wafer and we also see the beginning of front end moving to single wafer. At 32 nanometers we see all of the applications going over to single wafer at some of the customer sites. So by 32 nanometers we see the adoption going significantly higher than 50%.
So what’s our strategy to handle this market opportunity? First and foremost we want to deliver differentiated clean technology and we want to use our combined knowledge of clean in our spin and linear and plasma products to do particle removal technology, advanced drying solutions, use our knowledge in chemistry and fluid delivery, and create flexible integrated solutions. In some cases we already have the integrated solutions. For example, we already have the ability to do wet polymer bevel and back side bevel on the same system. We have the ability to do a dry plasma clean on an etch system, integrated in with an etch system. But as time goes forward we’ll be able to integrate linear technologies and spin technologies as well.
We want to reduce our cost of ownership and in doing this we need to improve the throughput of our systems and we’re working on delivering high productivity systems. We already have the industry’s leading productivity in our spin technology; I’m sorry, industry-leading throughput. We also are managing very specifically our chemistry costs which are one of the big cost drivers in the single wafer. We want to utilize the global support capabilities that we have, leverage the strong relationships that we have with our customers to offer and work with them in partnership to develop clean solutions that meet their needs in the future.
I’m going to go through now why there is an adoption of single wafer from batch. First this is just looking historically at the back end of the line post cleans and the back side bevel cleans. The main needs that we had in these applications were to have particle and defect reductions, improve selectivity which you can’t get in batch because of the long contact time, the long time that the wafers sit in a chemistry in a batch process, and also high throughput. And so if you look at batch processing, what happens when the wafers go down in the batch is that as they’re moved around in the batch system particles can transfer from one wafer to another so contamination in particulates can transfer from one wafer to the other.
And what you see now is a picture of a wafer from a batch with particles across the wafer. With the single wafer you eliminate that, you eliminate cross-wafer contamination in particulates. And we have with our DV-Prime we are the industry leader in single wafer cleans. And this is technology that’s been proven in production for many years on back side clean and also on back end of the line post cleans. And it is the highest available throughput today for single wafer clean.
At 45 nanometers as I’ve mentioned we see the introduction of the bevel-only into the cleans and what you need in bevel-only is selective film edge process exclusion control. What this means is that you need to be able to remove whatever you’re removing only at the bevel and not on the front of the wafer or in some cases not on the back of the wafer. And that eliminates batch from this application. And then of course also particle and defect reduction. If you look at a wafer now as we deposit films on it, what’s happening is the films are being deposited around the edge of the wafer and you can get poor adhesion of those films and they will eventually flake off and then redeposit themselves somewhere else on the wafer causing defects and yield issues.
With our Coronus system we’re able to etch those films and also remove the polymers on top of those films. And we are the leaders in the dry bevel clean technology and we have the flexibility to do not just polymer removal but multiple film removal with selective etching.
Also at 45 nanometers as I mentioned front-end-of-line starts the transition from single wafer to batch and that’s what’s driving most of the growth in the market between now and 2010 and the drivers of these are with the complexities of the structures and the high aspect ratios of the structures. We need to have damage-free clean, high selectivity to some of the new films that are being introduced at 45 nanometers and 32 nanometers, and also particle removal in these high aspect ratio features. So to show you a 45 nanometer post-metal gate, what will happen is there’s a significant amount of particulates that have built up on the side and also at the base. And when we’re cleaning we want to be able to clean these without etching into the structure itself or into the sub-straight.
With a batch clean and with long exposure to chemistries as you have in a batch clean, what will happen is the chemistries will actually start etching into the film stack and also start etching down into the sub-straight which would cause device performance problems. A second thing that happens in high aspect ratio features, you’re seeing a movie now of a megasonic bath. Bubbles will form and what they will do is then break and then crash and that will cause damage to the features. And what you see here is a picture of the type of damage that can happen in a megasonic clean.
So instead what you really want for these applications is a single wafer clean with short contact time. And with our DaVinci Prime and also with our linear clean we have the ability to have the flexibility of the amount of exposure time that the wafer sees to the chemistry and balance that with the particle removal. In the DaVinci Prime we have exposure times of about 30 seconds and then a Confined Chemistry cleaning, our C3 cleaning technology, we can do exposure times as low as 1 second to 2 seconds. So depending upon the application, whether you need long exposure time or whether it’s more important to have short contact time, we have the ability to do both.
Also in both of these systems we have world-class drying capabilities. We haven’t talked about drying yet but one of the problems that’s happening now in drying is you can leave water marks on the wafer and that also causes defect and subsequent film deposition problems. And so with both of our technologies we have advanced drying solutions to eliminate that.
So lastly, at 32 nanometers I mentioned some other front-end-of-line applications will come over to the single wafer area, and these are selective film edge, all wet cleans, and pre-cleans. And in general these applications need selectivity to underlying layers and they need defect and particle reduction. And this poses an opportunity for us with both our DaVinci Prime and our linear cleans. We have a very broad portfolio here and we can offer multiple solutions to be able to address those markets. And we’re working very closely with many of our customers to develop those solutions today.
So overall we have the broadest single wafer clean product family with our DaVinci Prime which is a spin technology, our Coronus with a plasma-based clean, and our C3 which is a linear clean wet technology.
From a standpoint of the market if you look at a number of the companies, memory, foundry and logic, we already have significant share in the backside in the bevel and in the back-end-of-line. We also have with our bevel-only significant penetration already in that area. And what we’re doing in 2008 is we are targeting key strategic customers and applications specifically to grow our market share in 2009 and beyond and we’re leveraging the largest install base that we have. We are the largest install base in single wafer cleans today.
In summary, we have the broadest portfolio of clean solutions for the single wafer market. We have technology leadership in single wafer cleans. We’re the leader in the established spin technology already. We have linear technology with short contact time which will enable advanced applications that require very short contact time for high selectivity to films that we’re trying to clean. We have advanced defect-free drying, drying without damage to the structures and drying without leaving water residues.
And for bevel we have the ability to do both wet and dry solutions; wet when you require polymer only and dry when you require a combination of polymer and film removal. As the industry migrates to 45 nanometers and especially beyond 45 nanometers, clean requirements are getting very difficult and new solutions are required to be able to meet these and provide clean defect removal without damaging the sub-straights, without damaging the devices. And we have the broadest hardware and process knowledge to be able to deliver those solutions to our customer base and we are optimizing these solutions through our shared knowledge of etch and clean interactions as well.
And the consolidation of our knowledge in the two companies, the SEZ and the linear group, with the hardware, the chemistry and our customer partnerships they’re enabling us to develop products specific for various applications and we’re just beginning to explore what options we have between our spin and our linear technologies to address these applications that are coming up. And lastly, we are positioned to grow our revenue and our market share in the single wafer clean area.
Now I’ll turn it over to Rick.
I’m going to talk about winning in etch and I thought a lot about what the title of this talk should be because I’ve used before and last year I used winning in etch continued. So I thought about winning in etch phase III but it sounded more like a Jaws movie than the semiconductor business. So I’m going to talk about winning in etch and I’m going to start off talking about the market growth opportunities that we see in etch and what our strategies are for taking advantage of those opportunities, and then most of the talk will be examples of how we’ve applied that strategy and capitalized on those opportunities.
So first of all this is a schematic illustration of the opportunities that we see in etch. So the center part of this diagram shows where we have been and the outer part shows where we’re going. And you’ll notice that in each segment of the business, and there’s dramatic change going on. In Interconnect for example copper metallization which of course that transition’s basically over in the logic arena is now taking place in a very significant way in the memory arena, and that’ll bring in more etch steps as well as creating just a new opportunity to grow etch market share. We have metal hard masks coming in as customers in logic move to porous low-k films and that requires different masking materials. That’s a transition that’s taking place in logic now and a future opportunity in the memory space.
In Motif engineering there’s a complete re-engineering of the transistor using metal gate and high-k films as opposed to polysilicon, silicon dioxide, and we’re now entering what’s called the fourth generation of strained silicon engineering and with each generation of strained silicon engineering new techniques are applied that increases the size of the etch market; new etches are introduced.
In patterning I think everybody recognizes now that there’s a big gap in the litho roadmap that after 193 immersion litho comes EUV but EUV isn’t ready and so semiconductor manufacturers must resort to double patterning. Double patterning can mean a lot of different things. There are a lot of different ways to do it. Spacer based double patterning is one that we’ll see going into production in the second half of this year and that entails more etches. And after that we’ll go into double exposure double etch and obviously that increases the etch market size.
We’ve talked before about the need to shrink. You don’t just double the pitch; you have to shrink the features as well and that’s something that we have a number of products available to do - Motif being a notable one. And hard masks have been used more and more. They help overcome some of the limitations of lithography, in particular line edge roughness, line width roughness. When it comes to density and scaling there’s a lot of talk about the end of the scaling and what are people going to do. And it’s not just lithography based; it’s a function of device architecture and circuit layout.
You get a lot of cross-talk between devices for example and how can you keep squeezing devices closer and closer together. So the solution is pretty evident and it’s to go from the two-dimensional world flat land into the three-dimensional space that we all live in already; whether that’s changing the structure of the transistor going from essentially a two-dimensional planar transistor to a three-dimensional transistor like a FinFet or changing the array. Today we have arrays of transistors that constitute a device in two dimensions and now we’ll see movement into the third dimension which offers an enormous increase in density and still maintains the bit cost scaling. And then there’s the three-dimensional aspect of packaging going from essentially single-chip packages to three-dimensional packages.
So what are the strategies that we’re pursuing to exploit those opportunities? First of all, and again we’ve talked about this in the past, is we want to exploit the learning curve. And by that we mean that we have a consistent commitment to technologies that have been winning for us and we don’t want to go in and completely redesign the reactor and force our customers to have to retool their existing fabs. And what that means is we give them a path if they do a Greenfield start where they can match the new fab with the performance of the old fab with low-cost upgrades.
That doesn’t mean we never innovate. Obviously as technology evolves and with all the changes that I described you’ve got to come up with new solutions. But our approach is to look at what matters most to the customer and what can we implement most cost effectively and preserve that installed base. We want to reuse knowledge. Any time you reinvent the wheel obviously it’s inherently wasteful and the net result is that we’re minimizing the customer’s risk of change and we create barriers for the competition.
We partner with our customers. We’ve talked about this before as well. There’s nothing better than getting the customer’s buy-in to your solutions and preserving or growing your share. And the best way to do that is to do a lot of R&D in their fab. And so we don’t have our own independent integration center. That forces us to partner with our customers, to put our engineers on site, with an upgrade strategy that’s built on an installed base. It’s a very natural way to go and it reduces the cost and time to solution both for us and for our customers.
The third element is to reduce cost of ownership. Jackie talked about this in the clean space. It’s been a core element of our strategy in etch for a long time. We’ve talked again previously about developing in situ solutions where you go through complicated stacks all in one chamber. It eliminates wasteful wafer transfer from chamber to chamber and reduces cycle time at the same time. It’s inherently the lowest cost solution.
All of our process development and our hardware development activities start with the premise that we’re going to provide our customers an in situ solution and they also start with “How can we upgrade the installed base and how can we make the option architecture sufficiently flexible given the complexity in the device technology that’s occurring and the diversification of the customer solutions? How can we tailor our solutions to their solutions?”
So a flexible option architecture is another key element of the strategy. And again the bottom line here is that this strategy significantly raises the barrier for entry of any of the new etch providers or would-be etch providers and anybody trying to penetrate a new application has a much higher barrier of entry because inherently they have to force the customer to retool the fab, which is obviously a very expensive proposition.
So let’s take a look at some examples. Let’s first of all look at Interconnect etching. I talked about the metal hard mask transition that’s stimulated really by the advent of porous low-k technologies. I’m not going to go into detail about that, just to say that there are some additional etches there. Instead I want to focus on the transition to copper metallization in memory which builds off what occurred already in logic and how Lam will take advantage of that opportunity. Strategy for winning: Exploit the learning curve. What does that mean?
So we go from a dual frequency capacity with coupled dielectric etcher to a three frequency capacity coupled confined plasma reactor, a pretty straight-forward approach and we were the first to market with three frequencies and it was a key to solving the profile control, particularly facet control at the top of the [inaudible], the intersection between the V and the trench and so directly relates to yield. At the same time we took advantage of the transition to expand our confinement window which essentially opened up the process window and improved the reliability of the product.
Reducing cost of ownership, we developed processes for dual damascene and copper or single damascene all in one trench in [Vea] solutions in situ processes and these solutions were available by upgrade. And that result is shown here in the application market share chart. So you see the customer’s down the left. Green means that we are the tool of record, either development tool of record or production tool of record. Gray means that customer hasn’t chosen to go to copper for that technology node and that device. And orange means that somebody else won. And that result is that we have a 75% application share in memory, copper, back-end-of-line today.
Moving next to Motif engineering, two major trends are strained silicon engineering. I talked about how we’re in the fourth generation. This latest generation is bringing three to five additional etch steps. And if you look at the metal gate high-k obviously you go from a very relatively simple stack to a very complicated stack and with that complexity brings additional etch market applications. Let’s take a look at the metal gate high-k situation. What was our strategy for winning, again, exploiting the learning curve.
In this case we’re using our conductor tool, the Kiyo based systems which use transformer coupled plasma technology as its core element but we first introduced wafer temperature tuning first in the industry and with our latest product Kiyo3X we’re now in the third generation of wafer temperature tuning and I’ll show you the results of that shortly. We also were the first to introduce advanced chamber condition control which I talked about last year and we’re now in the third generation of that technology as well.
As far as cost of ownership is concerned we etched this entire stack in situ and the feature set that enables our customers to do that etch in situ is available as a set of upgrade options on their installed base. And the net result is an application market share of anywhere between 55% and 80% depending on how some of the customers where we still have some competition, how that plays out of course.
Turning to the litho roadblocks and how do we get around the fact that there’s no EUV readily available and affordable. We talked about shrinks previously. We talked about hard masks. I want to talk a little bit more about double patterning. And when it comes to double patterning, whether its spacer based or double exposure double etch, the most important requirement is uniformity across the wafer and within die of the gate link. The uniformities compound with each step and so you have to have extraordinary uniformity compared to single patterning technology. So strategy for winning: exploit the learning curve.
Sorry if it’s getting a little bit boring but it’s I don’t remember which football coach it was, Vince Lombardi or something like that, that says, “If it’s working just keep doing it. So you run up the middle until the competition learns to stop you.” So we’re still running up the middle and they haven’t learned to stop us.
So it’s really the same technology that I talked about for metal gate high-k, it’s the third generation wafer temperature tuning. Actually we have a set of options. I talked about the option architecture that are tailored to different applications so there might be differences between metal gate high-k and the double patterning. And you can see here the bar graph is just showing the benefits of coming up the learning curve in terms of CD uniformity and we’ve consistently with each generation of product brought those numbers down. That’s what enables our customers to make yielding devices.
And today we have the capability of 1 nanometer range across a 300 millimeter wafer with 2 millimeter edge exclusion. And just to put that in perspective, you can see a picture of the silicon lattice here. We are really controlling things on an atomic scale over macroscopic dimensions. You can’t do that at any cost.
One of the big concerns our customers have about double patterning is the cost of double patterning with all those extra steps. So we’ve got to constantly be driving the cost down while we provide atomic scale control. And in this case the focus has been on; actually some of the non-critical or less critical etches, I’ve talked mostly about the critical etches, and so we have a different option architecture on our product that drives a lot of cost out. They don’t need all the bells and whistles for those non-critical etches. And again they can upgrade the installed base that they have and convert it to the double patterning set of applications. Looking at that critical application space today we’re sitting at 80% to 90% application share for the most critical etches in double patterning.
The last topic is going into the third dimension. Ongoing density scaling, and that means more etching. At the bottom here you see a transition from a 2D memory array; this is for flash; this comes from a paper published by Toshiba a little while ago, about a year ago; is based on trap charge technology and that may be more for the 2x, probably the 1x node. You have the 2D transistor going to a 3D transistor and then you have essential a two-dimensional package going to a three-dimensional package.
I’m going to focus on the packaging which corresponds to the release of our new product Syndion. And this 3D packaging is really enabled through silicon [Vea] etches. And our strategy for winning here in this case is exploit the learning curve, basically the product is derived from a combination of our polygate etcher, the Kiyo series, and our learning in the mem space where we’ve had good success in doing deep silicon etching using rapid alternating processes on our 200 millimeter Alliance product line.
So that learning was adapted as we modified our Kiyo product line and to Syndion. And then we added pulse low frequency for profile control. From a cost perspective in situ, in situ, in situ, I can’t emphasize that enough, this picture here shows a [Vea] last structure where you’re not; a lot of people just focus on the silicon etching and worry about how fast you can add silicon. It turns out the throughput of this process is not limited by how fast you can etch the silicon but how fast you can etch the dielectric and the metal that’s on top because the [Vea] lasts, by definition you’re drilling a hole after you’ve formed the device.
And this is actually where most of our customers are starting in terms of three-dimensional IC packaging is starting with the [Vea] last. They already have the devices and this is the fastest way for them to learn. We were the only ones that took an in situ approach to this application and it’s resulted in significant wins. And in order to deal with the throughput issue we modified; basically took our reactor and made some straight-forward modifications in an upgradable way putting higher power on the top to get higher throughput. And the net result is today we’re sitting at; it’s still an emerging market but we have anywhere from 54% to 80% application share in [TSV] again depending on how those competitive situations play out.
I talked about partnering and the benefits of partnering have been consistently recognized by our customers. This is a sampling of awards that they’ve given us over the last 12 to 18 months. So customers I think are recognizing the value of the offering from Lam. And the bottom line is that our strategy is working. We continue to win at the leading edge as illustrated here and you can see we’re winning across the board in all the market segments.
With that I’ll turn it over to Steve.
Stephen G. Newberry
I want to express my welcome to all of you. Usually when we gather here at Semicon it can either be a fun time as to where we are in the cycle or it can be a down time. Usually when it’s a down time it’s just us in the equipment industry who are lamenting our revenue and our profits and our share price. I want to welcome you to the crowd as members of the finance community you’re all lamenting your profits and your share prices this day. So we can all be a gathering of misery loves company convention because we are definitely in some miserable times.
A lot of you come to Semicon seeking answers to reasonable questions. By now you already know that there are no reasonable answers to the reasonable questions and we all think the same things. Relative to the short term the June quarter’s probably the order low and if not, surely it’ll be September. And hopefully we pray it can’t go as long as December but nobody’s going to guarantee it. And the reality is that we can all speak to what our customers say they think they are going to do, what our customers think they’re going to do and so therefore what we think we might do.
But the reality is that everything in this industry is so fast and it’s consumer-driven, it’s new product-driven, it’s new application-driven, it’s speed of technology advancement, it’s up the ramp yield curve, get down the cost curve. The supply chain to the semiconductor manufacturers starting with us and our suppliers are so short now and you can respond and react to whatever the situation is and the situation will in fact, no matter what we think, be different either better or worse.
So as a function of that I’m really not going to talk the rest of this afternoon while we’re here on what’s going to happen in 08. I want to talk about where I strongly believe the industry’s heading over the next couple years independent of what happens here over the next two to four quarters.
So I want to start with a view of 2008 so I’ll talk about semiconductor revenue and IC unit growth, talk about what I think the resulted wafer fab equipment spending environment will be, and as a function of multiple scenarios relative to wafer fab equipment spending what are some multiple scenarios for Lam revenue that we expect that we’re going to be able to exploit as a function of the strategies that Martin talked about in terms of what we as a company have been doing. So you can call that winning at Lam.
What Rick talked about, which was winning at etch, kind of part four or five because we’ve been talking about this consistently for many years as we have been talking about our company business model strategy for many, many years, and now we’re talking about winning in clean and applying our basic business model and strategies not only to the etch market but to other plasma-based products in those markets and now to the clean market and its opportunities. And so for a lot of you out in the audience you’ve heard these messages repeated over and over many times. Some of you have been to so many of these presentations you could probably give it yourself.
But there is a purpose behind all of that. One is we are totally consistent relative to our objectives and our strategies. You have to stay the course through good times and bad times if you expect to be successful in this industry. Martin talked about our continuous investment in R&D, our increased investment in R&D. I just got out of a series of meetings this morning with customers and what we talked about was this downturn could get worse and for most companies from a revenue standpoint in the September quarter it is likely to get worse.
If you’re a profitable company as Lam Research has been, we are not going to cut one dime of our investment in our core etch activities, we are continuing to invest in the other plasma-enhanced activities, and with the exception of the restructuring relative to the SEZ group that we acquired we are staying the course relative to our investment in clean. You can’t do that if you’re not consistently profitable.
So let’s talk about what the opportunities are for revenue growth and to be profitable. So what you see up here is semiconductor revenue forecasted to grow 2010, $310 billion to $340 billion, and IC units $195 million to $215 million. So we’re talking about IC units that on the low end would be about 8% compounded for the next couple of years; on the high end about 13% compounded. Right now we’re running and have been averaging for the last five years about 12% to 13%.
So there’s a conservative downside element to these numbers that I’m intentionally factoring in and certainly when we get into times like this people consistently over the years and over the cycles, they’re pretty pessimistic as to whether the future will ever be as bright as where we have been in the past. Yet historically every single time the future has been brighter and has been better, and I believe it will be again.
So let’s take a look at the next slide. This is tracking wafer fab equipment intensity investment as a percent of revenue. So it’s the same thing as CapEx, just stripping out the investment that’s not related to wafer fab equipment. So the yellow line that you will see is a 5-year moving average and if you go back to 2004 the five years included some very high investment years in 2000 and 2001, so you can see that the 5-year rolling average has been coming down and kind of stabilizing between 10% and 11%, kind of operated around 10.75% and then as a function of 2008 where we believe capital intensity will be, our wafer fab equipment tested very low. It’s going to come down to about 10.75%.
So in a conservative scenario for 2009, let’s say if wafer fab equipment investment intensity is only 10%, well below the historical average but certainly will be up from 2008 that capital intensity on the rolling 5-year average will be about 10.5%, still trending down. From that point we build a scenario that says, “What do we think is going to happen in 2010?” So we’re picking 11% which is where the average is over these last seven or eight years.
If you look at the 3-year rolling average you can see that it’s kind of been operating again through this year about 10.75% to 11% and if we invest on the low end then we’ll see the capital intensity average over the three years drop below 10%. If we invest at 11%, we’ll see it kind of move up right here on the continuation, this 5-year rolling average will be about 10.75%. And if you invested at 11.5%, you can cause the 5-year average to move up to 10.8% or so. So somewhere between 10.5% and 11.5% capital intensity which is not aggressive, it’s relatively conservative, causes the trend lines to really kind of stay below the historical average but still moving somewhat down is how we’re going to position this.
So the range of possibilities then based on 11% unit growth in 2010 from a base that you saw in 2009, $320 billion semi revenue. If you apply the 11% intensity you get $35 billion wafer fab equipment spending. So today if wafer fab equipment spending is $23 billion to $24 billion, a lot of people have a hard time believing that we can get this industry back to $30 billion, let alone $35 billion. But the reality is that if you think about the data that I just projected, if we get reasonable GDP growth, if we get reasonable IC unit growth even if it’s below the historical norms we’ve been running for the last five to seven years, it’s not very hard to get into this $35 billion range.
If we end up as a function of what the investment is in 09 and if we go back to the previous slide, you look at 2009 I’m only predicting that capital intensity goes to 10% of revenue and that’s not an aggressive revenue scenario. So it says fundamentally we expect that we’ll still be under-investing relative to the average. The more of that we under-invest in 2009, the more history says the following year in 2010 we’ll be even stronger so that the potential for an 11.5% or even a 12% is clearly there.
So with those numbers, what does that mean for the sale? If we go from 2006, $28.7 billion wafer fab equipment, our scenarios of $33 billion, $35 billion, $37 billion which equates to a compound annual growth rate of 3.5%, 5% and 6.5%, the traditional etch sale will grow right into this space here that you see it’s about 13% of wafer fab equipment could be slightly higher when you get into an accelerated mode by a bit. Single wafer $1 billion to $1.4 billion, centered on $1.2 billion. Patterning $250 million, and through wafer 3DIC set at about $100 million, so the new market SAM for Lam about $1.55 billion and our total SAM then grows at a compound annual growth rate that’s from 2.5 to 2.8x faster than the wafer fab equipment growth.
What does that mean for revenue? Well back when the market was $28.7 billion, Lam was $2.2 billion for etch and customer service business. If we hold market share and we’re still only in etch in systems; that’s the number you see on this line, if we grow our market share to 50% and Rick just showed you a slide that said at the 45 nanometer and the 4X flash and the 5X VRAM are application share is 50%. So we’re saying in this 2010 timeframe if we’re 50%, that’ll be a 5% incremental growth in etch market share from 2006, and there you see the incremental contribution from etch, so we’ll get the business up from etch and service to these levels.
Then if we are successful in that $1.55 billion market, we get 42.5% market share. Right now SEZ in the single wafer market’s running about 40% market share. And we’re expecting that with some of our other plasma-based technologies that we’re going to have that market share right in the 44%, 45% range. So we’ve been relatively conservative and said we’ll grow some market share in clean, we’ll grow some market share in some of the other arenas, and that coupled with some service business 7.75%, and so you see the revenues that we end up with. On the low end $3.6 billion, $3.855 billion, $4.2 billion, and in each case significantly greater growth on a compounded annual basis than wafer fab equipment.
And we’ve said going back three full years our target was to grow 2 to 2.5 times faster than the growth rate for wafer fab equipment. A lot of people have felt like, well, that’s not going to be very much because wafer fab equipment’s not going to grow very much. But I think what you can see from here is that even if you don’t believe that wafer fab equipment’s going to grow very much, because we are growing our SAM at such a faster rate and because the acquisition of SEZ has given us a significant speed-up in our SAM penetration for that market, then our ability to get to much faster revenue and therefore result in profitability growth rates exists.
So in conclusion, as Rick said, we continue to defend well and grow our etch market share. We’ve been doing that at each successive technology node. It’s not to say that we don’t have excellent competitors but we have been able to hold them off and continue to grow. The acquisition of SEZ accelerates our presence in the clean market. One of the things that people have been talking about for many, many years in the clean space, somebody needs to come into the clean space and consolidate it. The reality is that the best way to consolidate the clean space is not necessarily by buying four or five companies.
In my opinion the best way to consolidate the clean space is if where the growth is occurring is in single wafer, then go and acquire the single wafer market leader so the trends are moving in the direction you want; second, if the technologies it takes to effectively address the broad cross spectrum of applications that are available in the back end as well as the front end, you can own yourself as we do with the two significant models from SEZ, the linear cleaner revolutionary technology from Lam, and both the wet and dry bevel cleaners now have the ability to get all or substantially all of your single wafer cleaning needs at the most advanced technology nodes from one supplier.
Rather than believe me that this is important and it’s valid and the customer’s believe it, you have the customers here. Ask them whether they believe that with the broadest portfolio of technology capability that Lam has in the clean space now whether we actually represent that Holy Grail of a consolidated single point of supplier competence that the customers have been looking for in clean. I think we’ve done that.
So we’re going to continue to invest through this downturn for what we believe are significant opportunities for growth. How much of that growth will manifest itself and occur in 2009, I don’t know. We’ll talk about that as we go forward in time. The growth I just gave you all the scenarios for 2010, I think those are reasonable scenarios; I think there is an element of significant conservatism from a variety of the size of the market, the amount of equipment spending, and also our market share and the things that we could potentially do.
So we’re well positioned. I think that we continue to demonstrate to our customers that we are able to provide them with high productivity, unique enabling solutions to solve the kind of problems that Rick and Jackie talked to you about and we intend to continue to execute on the business model that Martin shared with you about.
So with that we’ll conclude the formal comments and we’ll be happy to take any questions that you might have.
We heard earlier today that you supply customers with about [inaudible] and I guess could you give a little color about how we could gauge your traction there specifically in terms of geography [inaudible] to give us an idea just how to gage your traction there and where those share gains will come from?
Stephen G. Newberry
I’ll comment just real briefly and then I think I’d like to ask Rick to go ahead and give you some specifics because I think that out of each technology node there are specific areas where the challenges increase. So the first part of our strategy is that we look at what our existing position is and we make sure that we’re working with the customer to defend that position. And then we go in and we talk to the customer about targeted opportunities where they have assessed that their needs and their risks relative to being able to get a high-yielding low-cost design are the highest. And then we partner with them on a selected basis.
So we don’t go in and try to go and penetrate all the applications that we don’t have. We go in and very specifically and very selectively do that and we have a number of areas where we have significantly grown our market share in memory dielectric. And if you’ll look at the slide that Rick presented, that’s been a very specific targeted area. This last year at the 45 nanometer node over the last 18 months we very specifically targeted certain applications in the foundry space that we felt like our solutions could be most viable. So Rick maybe you could talk about what some of the specific areas we’re targeting now that would give confidence that our market share capability is strong.
I think it’s pretty much what I showed. If you look at market share this year, a lot of the decisions in fact are made; you know 45 nanometers largely done and as Steve said we picked up some share on the back-end-of-line, logic and foundry, and we’ve continued to gain share in some of the applications in memory both flash and DRAM. But looking forward I think the biggest share gains are likely to come from the double patterning arena. That’s a big market growth opportunity in the next 12 to 24 months. Almost everybody’s, memory flash is going to go there first; logic is going to go there; and DRAM. So I think we’re well positioned and off to a fast start there. So that’s probably the single largest one.
The other area which is impacting, has impacted to some extent the situation at the 5X node and DRAM and going forward will have a bigger impact at the 4X node and certainly in flash 3X and 4X the transition I talked about in copper going into memory. And you saw the application market share position that we have. So that’s a very large volume market and actually represents a significant improvement for us relative to the position we had for aluminum metallization, be it aluminum etch or the dielectric etches around the aluminum metallization scheme, so we’re much better positioned in copper in the memory space than we were for aluminum metallization.
I had two questions, one maybe for Rick, when you look at the incremental etch steps for copper in memory, does it really matter if I’m a Japanese customer who actually used aluminum for the mask with metal liner keep an aluminum bond pad? Does the two to four incremental etch steps going from aluminum to copper get impacted by what kind of last aluminum step you use for copper?
Yes, of course it is but I think it’s very similar to the logic transition. So if you look at what happens in logic today; in fact most logic manufacturers, foundry manufacturers still use aluminum on the top layer, so I think the same thing will happen for some of the memory customers; not all. The transition still is towards an all-copper metallization down the road and I think the combination of copper on the device and then TSV where you start looking at the metallization which may be copper metallization with the through silicon B I have three-dimensional packaging I talked about will probably displace aluminum top level metallization over a number of years. But part of that application, the step growth if you will, the etch market growth in copper metallization in memory is just the recognition that you’ll need more levels as you shrink and increase the complexity of the device. So it’s similar to what happened in logic.
Unidentified Analyst 2
And along similar lines in the metal gate high K, does it really matter - how many etches does it make a difference to use like a gate first or a gate last kind of an approach?
We’re using steps a little bit generically because when you talk about an in situ process, one could call that one etch step and you go through that whole stack just like you would poly over oxide but if you look at the total thickness or the times associated going through that stack and the transitions that have to occur as you go from layer to layer and you’re changing your process conditions, that’s what leads to a lot of extra etch market.
In the case of the gate last approach, it’s pretty much a traditional polyetch so that’s sort of a one-to-one correspondence to the traditional polygate but then you have to remove the poly and so you have an extra etch step there. So probably I don’t think that we’ve looked at that too carefully but my feeling is that you’d have more opportunity in the gate first than in the gate last.
And the last question for Steve. You said you don’t want to comment on 08 but the last couple of quarterly conference calls you’ve spoken about the excess wafer sitting out there on the DRAM memory space. What’s your thoughts on where it was exiting the June quarter? Has it moved significantly from the March level? Is it still sitting around the same excess wafer capacity? If I remember right I think you said exiting March it was like 50,000 and 60,000 excess wafers on the DRAM basically just sitting out there versus about 70,000 exiting 07 I think.
Stephen G. Newberry
In terms of excess capacity?
Stephen G. Newberry
I think that from the standpoint of accelerating bit growth it’s occurred at a faster rate in the industry than what we thought and a lot of people thought because the conversion to 1 gig was faster and one of the things that was clear a lot of the DRAM companies were trying to do really starting the middle of 07 was find a way to softland intercept the tide of demand and slow down the rate of capacity expansion and try to hit a soft landing.
The problem is that when everybody kind of calculated what they thought the wafer starts were and how much of the product was 256 and 512 versus 1-gig, everybody said, “My secret strategy which I haven’t announced to anybody is I’m going to be the first to one gig. I’m going to be the first one gig high yield and I’m going to be the low-cost leader on one gig.” Except everybody was doing the same thing and so what you had was you were able to satisfy a lot of the bit growth with fewer devices and so therefore the wafer starts that they had still ended up in excess capacity.
So I think that the realization of that has clearly come home to people and I think over the last two or three months, the last couple of months in particular, we’ve seen a lot of customers I think just kind of basically throw in the towel and say, “Okay, that’s it. I’m pushing out what I had thought I was going to do anywhere from three more months to six more months.” The reality is once you push it, it doesn’t matter if they say three. It’s kind of going to stay in a push status until they can kind of see the pricing environment stabilize, so I think as we kind of talked about last quarter that we thought probably by the end of the third quarter you could kind of get to supply and demand parity. I think that that’s possible.
I think it all depends on the demand environment and I think given the general GDP environment, I think with weaker demand in China that what people thought, I think the reality is-is that the demand’s not going to hold up as strong. So my sense is that it’s more likely to be sometime later in the fourth quarter than what was thought about only two or three months ago.
Question for Martin, you talked about the [inaudible] $20 million restructuring charge in Q2. Can you help me understand what kind of expense reduction that you largely benefit from that in the September quarter in terms of OpEx? And for Steve, if I take that wafer fab equipment intensity chart of 10%, that works out to roughly 15% to 20% expectation from your end for CapEx growth in 09. Would you help me understand what sort of earnings potential that might have in the second half of next year with all the different moving parts? And if you could comment on just how bad September’s looking right now?
Martin B. Anstice
Relative to the restructuring as I mentioned we plan to report in the range of $15 million to $20 million of one-time costs. About a third of that is people related and two-thirds OpEx impairment related. And relative to the opportunity to lower costs as a byproduct of that action, if you do a June to September comparison the action will remove in the range of $5 million to $6 million from the cost structure of the company.
Stephen G. Newberry
So relative to kind of looking at what is CapEx intensity or [inaudible] intensity, I think that when you come out of a period of high investment, big losses, a significant drop in investment but continued losses in most of the segments, logic demand being relatively weak on the leading edge, although most companies will say that the 45 nanometer ramp that’s now starting is ramping faster than 65 did so they’re a little more bullish about what things are going to look like next year as opposed to kind of the whole adjustment factor for memory, the whole capacity productivity improvement plan in the Foundries, and then the big idea with logic guys is kind of there’s no business there.
So typically I think the spring-back is relatively muted in the following year because everybody’s a wounded warrior and all of their boards and shareholders are saying, “Let’s get some profitability back into this equation,” and I don’t think that we yet have recognition of a super demand driver that will overheat this thing so I think it moves up at kind of a steady logical progression that says “Look, if we’ve rung out all the excesses and we’ve rung them out of foundry, logic and memory,” that’s a good thing. It’s a painful thing right now this year. That’s a good thing. And it says now we can grow off of that base in a steady manner and even with a muted GDP we basically think GDP will probably be similar - 2.6% to 2.7% next year. So that’s why we think the level of spending will be about 10% from an intensity standpoint but it will be 10% of a somewhat muted semi revenue environment.
Although semi revenue can grow pretty rapidly if you can get ASP stabilization as you know, so it’s both of those things moving in sync with each other. But I do think that the next catalyst is, how fast do the flash companies get down to 64 gig, at what cost, and to the extent that they can do that, how does that translate into really driving the SEZ market? And as a function of that, we’re off to the races and a lot of people have kind of been moving around their forecast from as early as late 09 to as late as late 2010 or anywhere in between. I don’t really know when that’s going to happen but I would expect it somewhere in that vicinity.
And then clearly as people anticipate that, the real question in my mind is will the flash guys learn? Some of them are obviously the same guys that got burned in DRAM, that no matter how robust the demand is the supply chain can react so fast that even with 95% bit growth and DRAM off of a pretty huge base and 52% unit growth, this industry can over expand; no problem. I mean that upturn in 06 and 07; as equipment suppliers we did that with one hand tied behind our back.
So I think that’s told the flash guys, “Look, you don’t have to over expand to be able to output into rising demand. The speed at which you can get deliveries, the speed at which you can start up in qual and field is so fast.” And, I’m hoping that that’s the approach they take because that’ll mute the cycle and eventually they’ll get supply in front of demand and we’ll be cyclical again. But it doesn’t have to be to the same extent that the DRAM guys are dealing with it but we’ll see how it plays out.
In your 2010 model what part of the single wafer clean SAM is front-end-of-line? And same question for the revenue, what part of the new market’s revenue in 2010 is from front-end-of-line clean?
For the single wafer clean in 2010, it’s about 30% of the front-end-of-line clean SAM.
Is that on the market side or on the revenue side?
No, no. On the single wafer clean market side, just the front end.
And the new market revenue, what percentage front-end-of-line?
Stephen G. Newberry
We’re targeting that we want clean revenues to be somewhere in the $500 million vicinity and that’ll be a combination of revenues that come from the SEZ acquisition, from the Lam C3 linear cleaner, and the bevel plasma cleaner. And so like I said I think that if the market’s $1.2 billion for single wafer that we currently have a very, very strong and repetitive position in the backend and the opportunity is as the front-end-of-line goes from 5% single wafer to 30% single wafer that’s where the growth opportunity is. And so I think that we stand to be well positioned to do a revenue number like that.
And the $500 million clean revenue, which will that be? Like 50/50 between frontend and backend?
Stephen G. Newberry
What’s the mix between front and back?
Stephen G. Newberry
A lot of that depends on one, how well the frontend expands and who does the expansion and that’s being played out right now over the next six to twelve months as people make kind of 4X type decisions relative to certain frontend. It also depends on given the back-end-of-line position that SEZ has in the back-end-of-line cleaning, how well do we continue to defend and actually grow that. Second thing that it depends on is how many applications does the C3 go for. So I don’t really want to at this time try to break out the mix because I think it’s too many moving parts. One last question please?
I just wanted to ask Rick, in terms of getting the etch market share up to 50% you mentioned four of these big etch areas, which of those four areas that you mentioned do you think you have the best chance of gaining share in?
Well it depends over what timeframe. So the short-term opportunities as I said before are in copper metallization for memory and double patterning. The through silicon [Vea] market we think is going to take off over a longer period of time. And metal gate high-k; actually I didn’t mention that during my talk although it was in the title; the real opportunity there in our mind is when the metal gate high-k technology comes into the memory arena. Right now it’s mostly being driven by the logic manufacturers and that’s actually a fairly small market. But memory is going to go there probably 3X technology node maybe to some leading edge customers the 4X node. So when that starts to take off that market will become sizable. But the largest opportunities in the short-term are double patterning and copper metallization in memory.
Stephen G. Newberry
It’s been great to see so many familiar faces from the sell side as well as from the buy side. We appreciate you taking time out of your busy schedules here to spend a little bit of time with us. And we look forward to answering your questions as we go forward. So thank you very much.
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