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H. Bruce Campbell

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  • Slow Train Comin' - Micron, Intel And 3D NAND [View article]
    Thank you sooooo much William!

    And to mirror BenAround's astute observation of your astute observation, I wholly agree:

    "In the end, we're no better in our ultimate ignorance of all this than the "financial" guy, and at least he doesn't try to fool himself that he does know. We, on the other hand, are sometimes captive to our egos and this egoism can land us in some very hot water from an investing standpoint."

    I frequently offer my opinion that no matter how short we think life is, it's actually shorter than that. But no matter how sincerely I believe that - and I do believe it very sincerely - I still frequently behave as if I'll live forever - often I still fail to wring the most out of every day. Which is bloody poor utilization of my brief ride on the consciousness trolly since inestimable trillions of years of darkness starts quite soon.

    Try as we might, it seems borderline impossible to change longstanding patterns of thinking. Including of course the curse of our irrational egos... And with so much money on the table, we risk boiling hot water indeed!

    And yet we can't cower - we must act - no matter how short we think life is, it's actually shorter. And if we don't challenge our brains, and try to force feed new information to them by trial and error and joy and pain learning experience, our brains go numb and life ends up being even shorter.

    May we all succeed in finding an optimum balance between bold exploration and risk vigilance. And somehow weave a path around our egos, sufficiently setting that demon aside even as we maintain our quests for our dreams.

    And may the Chicago board of trade introduce 10 year term derivatives for public trade tomorrow...
    Jan 25, 2015. 04:45 PM | 6 Likes Like |Link to Comment
  • Slow Train Comin' - Micron, Intel And 3D NAND [View article]
    Thanks Growlzler! Again your insight and perceptions make perfect sense to me, and provide valuable guidance.

    I absolutely agree for example that "The caveat is that the future always takes longer to arrive than those involved think it will. The knack is getting the "when" part right. This is not "market timing" it is technology application timing and requires more than a little work to get it right."

    I frequently wish I could purchase quite long term call options - ideally with expiration dates similar to those designed to incentivize corporate officers and key employees. The longest term we common investors can acquire, about 2.5 years, just isn't adequate for many or perhaps most ground breaking technology developments to mature to undeniable profitability. So we're stuck in the awkward position of wanting to partner our leveraged money with great R&D, but having no access to derivative time frames which are genuinely suitable for the real time frame such investments require since new technology usually takes more than 2.5 years to sufficiently prove its mettle to the investment community. But we do at least have the common stock alternative, and the allure of leverage notwithstanding, I still covet all my common shares as if my daughters and sons. But I wish the ordinary derivatives market would expand to include much longer terms, and suspect it might be healthy for the market as a whole too. Maybe...

    Your references and others in this discussion overwhelmed my pace of study, and will likely continue to do since many interesting references open doors to several others.

    The Cadence hosted "MemCon 2014 Samsung Keynote: DDR4, TSVs, and High Bandwidth Memory (HMB) Will “Transform” DRAMs" summary you (or someone here) referenced at was particularly interesting. Taking it at face value leaves the impression that Samsung's already established a formidable lead in new memory and storage technologies. A snippet, very slightly edited, is:

    'In August 2014, as Tabrizi noted, Samsung announced that it has started mass production of the industry’s first 64 GB, DDR4 RDIMMs that use 3D TSV packaging technology. The new RDIMMs include 36 DDR4 DRAM chips, each of which consists of four 4 Gb DDR4 DRAM dies. According to Samsung, the new 64 GB TSV module performs twice as fast as a 64 GB module that uses wire bonding, while consuming half the power.

    This is Samsung’s first TSV product. “I think it will be great for high-density applications,” Tabrizi said.

    Meanwhile, Tabrizi said that Samsung is looking into HBM. “We can increase performance by almost 80%, and reduce the power quite a bit,” he said. “We can achieve 512 GB/S and can have as many as 1,024 I/Os. Just imagine what engineers can do with that wide data path.”'

    Tabrizi also evidently said something akin to '...and called on the DRAM and NAND Flash communities to work together to support the [voracious] performance, power, and density requirements of “big data” in the cloud.'

    I find it difficult to form an opinion about Samsung's real position in these areas - given their recent history with 3D V-NAND, it's only natural to be skeptical of whether the other very lofty sounding developments are genuinely credible. However, Samsung's a very tough competitor with a lot of fire in its belly, and not to be dismissed of course, even if their enthusiasm outpaces their actual results from time to time. (Captive to my ego and over-excitable, I'm frequently similarly flawed.) We all want to know where Samsung really stands with these technologies, but divining such information isn't easy.

    I've never so much as touched any semiconductor fabrication equipment, and thus I'm at a significant judgment disadvantage to several in these halls. Presumably advanced fabricators operate at the limits of precision and nuanced control of numerous parameters all the time, and given the near atomic dimensions involved are constrained by difficulty in seeing what's happening as parameters are ever so carefully adjusted in a quest for optimum and consistent results. I'm purely guessing that sufficient consistently of results is a key factor which might be the most elusive of all.

    Given Samsung's 3D V-NAND history, as an investor I have to wonder whether the firm's chronically inclined to be overoptimistic about its ability to produce consistent results, and thus whether to judge Samsung's public statements about its new technology capabilities skeptically.

    In my limited personal experience Korea's a fascinating place with truly stunning infrastructure accomplishments, and I enjoy my visits. But in some respects the air there is relentlessly tense, at least partially for the obvious northern reasons. Business competition seems to produce fruitful outcomes, but is fierce, and not always constructively so. Business integrity isn't perfect anywhere of course, but personally my sense of skepticism is stronger in some cultures than others, and I generally watch my radar screen more closely when Korea's involved. Presumably none of this is news to anyone here of course...

    But I just don't have enough Korean experience, nor experience with Samsung in particular, to be competent in judging Samsung's public statements about its semiconductor advances. Nor have I studied details about actual Samsung shipments of their most advanced memory and storage products, nor their customer's satisfaction level with their performance and value.

    I'm almost wholly ignorant about Taiwan culture, but consistently hear praise about Dr. Morris Chang's integrity and skill. So I'm inclined to reasonably trust publicly released information from TSMC. But currently Samsung seems like a far larger factor in Micron's fortunes, and I just don't have much personal confidence in judging them.

    Which, at long last, leads to this question for everyone here who cares to comment: What's your opinion of Samsung's claims as revealed by the link above, or other relevant claims - do you think they're reliable, or generally premature, or even just wishful thinking? Or perhaps more to the point, in the sprint involving Micron, Intel, and Samsung, please offer your appraisal of the race. And if you know of any trustworthy external play by play commentators, who are they?

    I'm very interested in opinions. And wish I had a talent for requesting them in a concise manner...
    Jan 25, 2015. 04:10 PM | 2 Likes Like |Link to Comment
  • Slow Train Comin' - Micron, Intel And 3D NAND [View article]
    Thank you soooo much Growlzler! All the technical considerations make perfect sense to me.

    But I wasn't aware that Micron people were openly saying "...and that's not the only thing you can stack", and I absolutely agree that it's "more than just a hint of what the company has planned for the technology".

    What baffles me is that the investment community at large (excepting some mighty sharp cookies in these halls) seems blind to this technology inflection point. It's no small matter and will, in my estimation, very heavily influence great corporate fortunes. I've been pounding the table about it for two years, but it still doesn't seem to get much focused attention. Which seems very odd to me...

    Everyone has their own investing style, including time frames of course. And even the most remarkable and important technology inflection points don't always spell success for the firms which introduce or champion them. But investors should heed the developments anyway, and invest according to their perception of which firms will be able to make the most hay from eyebrow raising new technology advances.

    Nobody should blindly follow anyone else's perceptions, including God forbid mine. But I think everyone should consider what's happening with Intel and Micron very, very carefully. Semiconductor technology is entering a bold and remarkable new era - a true technology inflection point. For the first time semiconductors are becoming true three dimensional structures, and in two ways (die stacking and repeated deposition and etch). We just left the starting blocks in a race toward a modern incarnation of the SHGB (Smoking Hairy Golf Ball) ideal processor dream. It's truly amazing.

    In my estimation the implications for consumer products are immense. And holy cow, far wiser data sieving technology as you described leverages new ITech advances dramatically further. Intel and Micron are very deeply involved and very aggressively pursuing both inflection points. Other than lucky home runs in a wild gamble, does it get any better than this for investors?

    I can't speak for anyone else, nor do I want anyone to follow me blindly. But I won't be investing any of my money in a utility nor toothpaste company in the foreseeable future. I'm never perfectly comfortable with any investment, but at this time I'm at maximum comfort intensely focused on Micron and Intel. To me the question isn't, for the most part, one of success or failure. To me it's primarily just a question of timing (such as will these matters finally sink in for the investment community at large before my January 2017 options exercise?).

    I can't adequately express my personal gratitude to everyone contributing here, and William of course for the springboard he erected and nurtured. This is the most fruitful and civil conversation I can remember in my entire personal experience. I'm deeply grateful, and I hope it continues.

    (And I hope I'm not destroying it with my galaxy class inability to be concise.)
    Jan 24, 2015. 02:57 PM | 5 Likes Like |Link to Comment
  • Slow Train Comin' - Micron, Intel And 3D NAND [View article]
    For most here I'm stating patently obvious facts below, and thus this comment is useless and will just waste your time. But in case any confusion develops among investors with less electrical engineering background:

    Photons don't solve communication delay problems - ITech (Intimacy Technology) pressures can't be eliminated no matter what communication physics is involved. In a race between a beam of light in a vacuum and an electrical signal in a superconducting wire in a vacuum, the result is a tie - they'll both reach Proxima Centauri at the same time - after about 4.3 years. Or in a race from the base of your index finger to the end of your index finger, they'll both reach the tip of your fingernail in about one 3 GHz processor clock cycle.

    An electrical signal in mixed materials (an ordinary copper conductor resting on a solid material for example) is slower, but not dramatically so - the speed of light in a vacuum is 299,792,458 meters per second. The speed of an electrical signal in mixed materials is very roughly 170,000,000 meters per second, or about 57% of the absolute Cosmic speed limit.

    Photonics is bloody cool and solves some major problems, but photon communication doesn't put so much as a dent in the need for ITech. Data center and other data infrastructure design and high performance consumer device design face different scaling and performance challenges. But both must wrestle with signal speed limits (whether electrical or optical).

    In consumer devices the major performance metrics are optimized by squeezing all components into the tightest sphere possible to minimize physical communication distances (and energy consumption). Or, near term, cubes, because they're more natural structures for current fabrication technology.

    That can't eliminate latency associated with communication with the infrastructure - if your device requests data from a server in Hong Kong, it still has to wait a very long time to complete the request / receive cycle - very roughly 100 mS (plus delays due to router and server performance limits).

    But ITech does enable your device to perform all its local processing, control, and display functions faster, thus providing a more pleasing user experience. And photonics, as cool and useful as it is, doesn't change that reality.

    Whether optical or electrical signals, the modern challenge is the same - reduce all signal path lengths to the shortest possible distances. In either case we must still press forward with ever better ITech.

    Sorry to utterly bore most of you - I mean no disrespect of course.
    Jan 24, 2015. 11:17 AM | 3 Likes Like |Link to Comment
  • Slow Train Comin' - Micron, Intel And 3D NAND [View article]
    Okay! And all solely at my own personal risk of course.

    I'm still excited though...
    Jan 24, 2015. 10:58 AM | 1 Like Like |Link to Comment
  • Slow Train Comin' - Micron, Intel And 3D NAND [View article]
    Wow Blue, wow! That Dave Bowman quote isn't lost upon me (I read and absolutely loved the book too), and hearing such comments prompts me to mortgage my home, car, tractor, lawnmower, and shoes to finance purchase of more Micron calls.

    Jan 24, 2015. 09:10 AM | 4 Likes Like |Link to Comment
  • Slow Train Comin' - Micron, Intel And 3D NAND [View article]
    Wow Growlzler, thank you so much! Every time I think I'm establishing a grip on things, entirely new rooms of complex matters open before me. Lots to study here...

    Do you have any idea how the “Silicon Photonics” bridge is typically implemented? That is, is it integrated into the processor such that the processor package has both electrical and optical terminals (seems feasible, but I've never heard of such a processor), or is it a separate bridge chip implemented in a separate package (and thus, I'd think, its communication with the processor subject to unfortunate bandwidth limitations and greater power requirements than would be possible with a TSV or stacked photonic connection for example)?

    Another note: In my last prattle I inadvertently and indirectly implied that a processor would have to be equipped with TSVs if electrically connected to a TSV equipped cube such as an HMC or HBM (High Bandwidth Memory), but that's not true. Assuming the processor's positioned at the bottom of the assembly such that cubes are stacked on top of it, the processor need only have rather ordinary bonding pads which dimensionally mate with the TSVs in the cubes stacked upon it to complete a direct electrical to electrical connection - there's no need for TSVs in the processor itself.

    A photonic connection might still be preferable, but not because it would eliminate a need for TSVs in the processor - no TSVs are needed in the processor in either case. If a photonic connection's advantageous, my guess is that it'd be because it might eliminate a need for a SerDes layer - the communication channel could be a faster direct parallel to parallel connection. Maybe - I'm just speculating with minimal contact with the active design community.

    Irrespective of how dramatic these concepts prove to be for the data center sector, my guess is that they'll ultimately define winners and losers in the consumer and portables sector. I continue to believe SCs and Balls are coming, and will nestle in all our pockets some day.

    But I could be wrong of course, as I often am...
    Jan 24, 2015. 09:00 AM | Likes Like |Link to Comment
  • Slow Train Comin' - Micron, Intel And 3D NAND [View article]

    Regarding "...Intel is in a position, eventually, to put the SSD in the CPU package." Agreed, but in my view a later option is: '...Intel is in a position, eventually, to put the SSD on the CPU.' That is, marry the two with TSVs. Or optically. I'm practically blind, but elements of the comments here seem to suggest that in the case of memory (rather than storage), the progression of events might lead there. Eventually at least... And it seems to me that storage will follow an Intimacy Technology path blazed by memory. And rather rapidly.

    Oak8292 said: "One apparent problem with HMC is the lack of interconnects to servers. Intel is not an 'adopter' of the HMC standard as it appears that they want to roll their own logic and use photonics in the connector for the Xeon Phi. It appears that Xilinx and Altera will be the only Micron HMC 'adopters' in 2015. There is interconnect IP available for the TSMC 16nm process which may or may not indicate that it will show up on a processor this year."

    Then he said "Obviously Intel has a communication channel with their Xeon Phi implementation of 'HMC'. However, I can not find that anybody except Intel that can connect a Micron HMC to an Intel processor. Eventually Intel must provide the actual Micron HMC compatible SerDes channel on the processor if this is to be more widely adopted anyplace other than the Xeon Phi." [SerDes: Serializer/Deserializer, a transceiver which converts parallel data to serial data and vice-versa.]

    Then Growlzler said "Oak8292 gets a gold bingo award - Arista and DSSD is the integration glue that holds this all together. Why was HP in talks with EMC (now owns DSSD) or why does Diane Bryant behave like a teenage girl in love when on stage with Andy? Wonder no more...,"

    (Arista products: And from "DSSD designs and builds innovative rack-scale flash storage. DSSD’s architecture complements EMC’s industry-leading flash storage portfolio and delivers game-changing performance for I/O-intensive in-memory database and Big Data applications such as SAP HANA and Hadoop." However, the "...why does Diane Bryant behave like a teenage girl in love when on stage with Andy?" went right over my head, so I'd be very grateful if Growlzier or anyone else would clarify this. And their family relationship, if any (none that I'm aware of).)

    Then Ol' Kiddy Shrink, reporting on the investor meeting, said: "Subsequent to the formal presentation I cornered Mark Adams the president of Micron. He and Brian Shirley answered questions about the hybrid memory cube. They indicated that it is currently in the marketplace and has received excellent reviews from the high power computing and networking communities. They indicated that sales of the hybrid memory cube would impact the earnings late 2015 and early 20[1]6."

    Wow, the HMC is expected to "impact earnings" starting late this year! Wow...

    Frankly I simply don't know how to connect these dots confidently. But it sure appears that HMC equipped Data Center products are nearing production (late 2015 ish). Which, as Oak8292 said, implies that a Xeon Phi to HMC communications channel must exist. It seems to me that its physical layer could be utterly custom - there's no requirement for the physical layer to meet any standard - maybe Intel and Micron simply cooperatively designed a physical layer which optimizes communication between a custom Micron HMC and the Xeon Phi specifically. All the better from both Intel and Micron's perspective - in a data center landscape which Intel dominates, why embrace any JEDEC standard physical layer which would make a competitor's entry into the sector easier? A custom physical layer gives the Intel / Micron partnership an opportunity to dominate with a highly custom design as if they were a single monopoly firm, yet remain legally separate, hopefully keeping DOJ eyebrows from rising. Arista, DSSD et al presumably complete the Xeon Phi / HMC marriage with refined communication protocols - the "integration glue". If I understand correctly...

    Initially my guess was that the physical layer wouldn't be an optical bridge unless the Xeon Phi and the HMC were rather distant from each other - it seems to me that over short distances the increased power and delays associated with conversion of signals to optical then reversion back to electrical would render an optical bridge less efficient than simple direct electrical connections (that seems like the simple physics of the matter to me, but critique please). The current push is to locate every functional block as close to every other functional block as possible, so I doubt there'll be much space between the Xeon Phi and the HMC in these systems. So I was skeptical an optical bridge would involved.

    Again however, Oak8292's said " appears that they [Intel] want to roll their own logic and use photonics in the connector for the Xeon Phi." Oak8292 has my respect. So, personal skepticism notwithstanding, I suspect some optical intrigue's afoot.

    And that dot seems to me to potentially connect as follows: A SerDes introduces communication delays too of course. So suppose Intel discovered that a parallel optical bridge between a Xeon Phi and an HMC was the highest performance option because the optical emitters and receivers could be very tiny, cause no more communication delay than a SerDes (and maybe less), and need not involve any intermediary optical pipe - instead, drum roll please, they envision physically stacking the HMC directly on top of the Xeon Phi with each one's optical components directly facing their mates on the other die.

    Thus there'd be no direct electrical connection between them, and thus no need for TSVs in the Xeon Phi. And the physical structure holding the Xeon Phi and the HMC together would be very simple, fully reliable, and serviceable - just an alignment frame and a gentle spring clamp (plus perhaps a bit of transparent paste). And the parallel communication performance between the two would be superb in both speed and power efficiency.

    It's just wild speculation of course. But I have to wonder why the devil any hint of an optical bridge for the Xeon Phi would enter any conversation otherwise - I can't imagine anyone's really considering provincial optical fiber to connect a Xeon Phi with an HMC (except*). Besides, why do so? If they can simply be stacked, a far more elegant and higher performance system would result. If there's a technology barrier, I fail to see it. (However, I'm not practicing in the field of course, so I'm not genuinely privy to the deeper engineering details.)

    And if that makes sense for a Xeon Phi / HMC marriage, why not add an SSD the same way? (Perhaps in the form of a TSV equipped stack of 3D NAND die.)

    And if such a design proves practical for a Xeon Phi based system, why couldn't an Atom be equipped with an HMC and SSD the same way? If the economics of TSV equipped HMCs and SSDs are good enough for consumer products... (But remember the Atom itself needn't incorporate TSVs.)

    Maybe something like that's afoot. But I'm very eager to hear everyone's opinions. Because I could be completely wrong of course - it's just wild speculation after all.

    (*Except in cases where the shear magnitude of storage is so large that it's not physically practical to stack on a processor, even when fabricated with 3D NAND. But then an optical communication bridge still makes sense, but using optical cables, and capable of a higher drive power level since the optical emitters must overcome optical cable losses. So maybe there'll be two versions of Xeon Phi: One with low power optical emitters, and one with higher power optical emitters. Or just one which can throttle its optical emitters as required.)

    If I did miss something - something fatal - and thus my dot connections above are just completely wrong, then I fall back to more pedestrian thoughts:

    Rather than utilize an optical communication system, to me it seems more likely that a proprietary Xeon Phi and proprietary HMC will be located in very close proximity and communicate solely electrically.

    Presumably within a conventional single package in initial products. But then later stacked using TSVs to interconnect. Okay, I know that's a stretch at this time. And it would be an odd looking stack since the HMC block would, I presume, consist of dimensionally smaller chips than the Xeon Phi (but for the most part that's of no practical consequence so long as they expand and contract reasonably in unison). Highly unlikely now I suppose. But not impossible. And perhaps ultimately inevitable, simply because a stacked structure would provide higher performance at lower power. (As would a Xeon Phi with TSV equipped HMC and 3D storage both stacked on top like two freight containers sitting on a barge - if storage capacity requirements aren't overwhelming.)

    To me the "...sales of the hybrid memory cube would impact the earnings late 2015 and early 20[1]6." is a pretty bloody dramatic Micron statement. I don't know what their sense of proportion is when they say "impact earnings", but it was an investor meeting after all - I wouldn't think they'd use that term in conversations with investors unless the impact was meaningful. The notion that the HMC might be a meaningful proportion of Micron earnings this year and next strikes me as a rather substantial trek along the cusp of a technology inflection curve which has rather dramatic implications for both Micron and Intel. And their competitors too unless they're prepared to pull a whale of a nifty rabbit out of their hats. I don't mean to suggest the HMC will be directly stacked to a Xeon Phi this year, but I suspect they'll be side by side holding hands. Then a bit later become intimate - maybe, just speculating wildly, in 2016.

    Extending this theme further, if TSV fabrication is now reliable enough to design into data center products, then it's reliable enough for consumer products. Cost is a whole different question of course - consumer products must be far cheaper to fabricate. But speculating, suppose Intel, which is spending billions to try to wedge itself into the portables market, were to propose SC (System Cube) products for iPhones and iPads to Apple. With performance levels Samsung simply couldn't reach by a wide margin. Even if Intel just broke even on the business initially, I think they'd find it alluring. In part because it would provide substantial TSV fabrication experience which might lead to economical and more technically refined TSV technology. Within Intel's exclusive walls, to be added to their 14 and 10 nm trophies.

    One last matter (God I'm sorry to be so verbose):

    Growlzler also said "An item that disturbs Intel the most is the fact that the data search function is moving away from central processing to a distributed one performed near the data in a massively parallel fashion - hence Near Data Processing (NDP). Micron is only too aware of this shift in computing architecture and has made public the Automaton Processor - an anticipatory device. Computer architecture in short is moving and away from the central computing model toward a data centric one much to Intel's chagrin."

    That makes perfect sense to me, at least for the infrastructure sector rather than the portable sector. But insofar as the Intel / Micron relationship is concerned, I view unique strengths as a recipe for strong partnerships. I'm no student of successful marriages, but the healthiest I've witnessed have been those in which each partner had unique personal strengths, and each genuinely respected the other. It's just a foggy judgment of course, but, with the DOJ hovering in the background (albeit with national security politics occasionally tweaking DOJ's reins), and Micron and Intel each possessing unique strengths in spite of their substantial size differences, my sense is that the partnership has a terrific foundation, and the brass of both firms are highly motivated to make the most of it. Each needs the other. And respects the other. It seems like a very productive and healthy relationship to me. And hopefully long lived.

    Everything changes of course, and eventually some stresses will build and cause serious problems, or they'll simply drift apart. But for the foreseeable term, including the technology transition to SCs and Balls, I suspect the partnership is more than strong enough thrive productively for the distance, particularly with a DOJ nanny hovering about. At lease I hope so, because my leveraged chips are on their squares. And besides, I love the excitement of advancing tech...

    I'm just speculating about all these things of course - all investors must steer their own ships...
    Jan 23, 2015. 09:59 PM | 6 Likes Like |Link to Comment
  • Slow Train Comin' - Micron, Intel And 3D NAND [View article]
    Wow Ol' Kiddy, what a superb review! I feel far more genuinely attached to the sense of events on the ground now. Three cheers, and thanks soooooooo much!

    The realities of what's happening now make those things which seem likely to happen later seem ever more tangible. The future is so tantalizing I can almost taste it...

    Intensely long Micron common and calls, and Intel calls, and moderately long Intel common. And now feeling even more comfortable about it.
    Jan 22, 2015. 07:46 PM | 3 Likes Like |Link to Comment
  • Slow Train Comin' - Micron, Intel And 3D NAND [View article]
    Hi Bruce,

    Considering his far superior immersion in current events and technology, William addressed your questions in his second comment under his article much better than I can. I wasn't aware of the possibility of an Inotera negotiation failure for example - I know nothing about what's afoot there, but given William's comment the matter worries me a bit. But only a bit until I know more...

    Compared to many in these halls, I'm just an overly chatty empty shirt. So I defer to everything William said in his comment, except to add my take on trading mechanics, and a wider perspective (but if William and others add their views about these too, we'll all be far better enlightened):

    My personal sense is that the very heavy institutional holding of Micron common causes unusually forceful derivatives pressures on Micron's stock price, and thus it seems more likely to get tugged to the prices illustrated by the Max Pain charts, and pinned to even dollar or 50¢ price multiples, especially on Fridays. But of course important fresh news often overwhelms derivative pressures, at least for a while.

    For the wider perspective, I like to think Micron and Intel currently have more fire in their bellies than most or perhaps all of their competitors. But that's bloody tough to judge of course. But in any case semiconductor technology seems to be on the cusp of a transition to effective elimination of provincial communication distances. That is, by one means or another fabricators will squeeze everything into one cube or ball, whether of stacked die or stacked deposition and etch, or both, reducing all internal system communication distances to a few millimeters at worst, and Angstroms at best.

    Presumably every significant step along that path which yields substantial performance improvements will prompt some measure of a global product refresh cycle as usual. And as you've so eloquently described, IoT seems likely to spring forth like a technology geyser - though far cheaper, such products will likely also become far more ubiquitous than cell phones, potentially creating a similar value market. Maybe...

    Other substantial new product classes await their exponential growth curve cusp too, perhaps including my favorite, consciousness technology class devices which continuously compare real time sensory information to past sensory information held in storage, and continuously process the comparisons to discern higher order information, just as we do when we're awake. Current technology seems akin to us when sleeping - in both cases the now / past continuous comparison process isn't functional, and thus consciousness doesn't exist. But when awake we are environment and self aware. As will be such devices in my opinion. I suspect this technology is closer than most believe.

    If Intel and Micron can at least maintain their positions as major players during these technology advancements, they should earn a lot of money. So I hope they do indeed have a lot of fire in their bellies...

    I'll send a private message about my feelings about Micron calls because I've already posted far too much insipid babble here. (Sorry William and everyone.)
    Jan 20, 2015. 07:13 PM | 5 Likes Like |Link to Comment
  • Slow Train Comin' - Micron, Intel And 3D NAND [View article]
    Thank you soooo much Oak8292! Fascinating information. I was unaware of the site, which appears to provide a lot more information than I was able to find earlier (my study effectiveness leaves a lot to be desired). I'll peruse it and relevant links in more detail as time allows.

    (It seems a shame to me that "3D" is being utilized as a moniker for TSV enabled chip stacking. That creates rhetorical confusion with deposition and etch based microscopic 3D, and strikes me an unfortunate intrusion on microscopic 3D's rhetorical turf.)

    Thanks tons for your other insights too. It seems odd to me that Intel appears to prefer photonics for the Xeon Phi rather than an electrical connection, but of course I'm in no position to judge the tradeoffs.

    However, if an important firm, like Apple or Samsung for example, manages to arrange practical and economical fabrication of an SC before Intel does, Intel had better have something at least competitive available by that time. Perhaps it's too far reaching to suspect that TSMC's TSV interconnect IP is a hint that some firm's engaged in design of an ARM based SC. But that doesn't seem impossible so far as I know. It seems to me that an impressive ARM based SC would be mighty big trouble for Intel, potentially sending their efforts to penetrate the mobile market right back to square one. Among other serious problems...

    Perhaps I can count myself among frustrated TSV enthusiasts. I don't know enough to judge whether the slow progress is due mostly to current TSV fabrication economics, or to lack of IP, or both. My guess is mostly the first - otherwise I'd think the second would be well funded and aggressively developed. But currently I simply don't know - I need to read more, and temper my fears in the last paragraph until more of the many moving parts become a bit more clear... Thank you so much for providing a terrific place to start and your other insights!
    Jan 20, 2015. 01:54 PM | 4 Likes Like |Link to Comment
  • Slow Train Comin' - Micron, Intel And 3D NAND [View article]
    Hi Currant85,

    TSV and 3D are completely different things:

    TSV is a conductive hole bored through the silicon die which provides a connection from the front side of the die to the back side of the die ( With both front and back side access to the circuits, die can be electrically interconnected in stacks like pancakes, making die to die interconnectio exceptionally intimate, which enables far faster communication at far lower power levels. That's why the performance of the HMC is far better than any other currently available memory technology.

    3D is unrelated. It's a circuit fabrication process involving repeated deposition and etching of circuits on the top of the silicon die, creating layers of circuits, one on top of another. But on only one side of the die.

    In effect both are three dimensional fabrication technologies, and in both cases part of the goal is to vastly improve ITech (Intimacy Technology). But otherwise they're unrelated approaches with their own unique advantages and limitations.

    TSV's hope is that all sorts of die can be interconnected in stacks, creating cubes containing processors, memory, storage, radios, and whatever else a system needs, with all functions in direct die to die contact so that communication distances are very short (just a few millimeters at most, and usually much less), and thus communication speed very fast, and communication power very low. And the die in the stacks can be of any fabrication process type, and sized for exceptionally high fabrication yields, and thus very low fabrication cost. The HMC is a TSV equipped structure.

    3D's hope is that a deposition and etching process can be repeated over and over, each on top of the previous, creating direct layers of microscopic sized circuits with microscopic sized conductive column interconnects, all residing on top of the die. But 3D itself provides no TSVs, and thus the die's circuits remain exclusively on one side of the die. However, those circuits are the most intimate of all - they are true microscopic sized three dimensional circuits. But the fabrication challenges are such that there's no moderate term (perhaps five to ten year class) hope that differing fabrication technologies, such as are involved with memory, storage, processing, and radios, can be fabricated together in a 3D structure - the process is currently limited to a single fabrication technology, and is still no walk in the park.

    Nor is fabricating TSV's a walk in the park. Both are difficult. But immense rewards await success in either case, for these two rather simple reasons:

    Due to Mother Nature's ultimate speed limit, the speed of light, in the time it takes a 2 GHz processor to execute a single clock cycle, a signal in mixed materials can travel only about the distance of your index finger. In the world of high speed information technology, an index finder is an intolerably vast distance which causes intolerably long communication delays and intolerably high power requirements. ITech, which includes 3D, TSV, and other advanced work, is the art and science of minimizing communication distances, and thus reducing communication delays and power requirements. It's Holy Grail from decades ago is the SHGB (Smoking Hairy Golf Ball).

    The time delay problem is relatively self evident. Regarding the power problem: Due to parasitic (capacitive, inductive, and resistive) losses, the longer a signal path the more power required to drive the signal. ITech addresses that very serious issue as well - when communication distances are just two or three millimeters long, such as in TSV interconnected stacks of die, communication power requirements are feather light. And when communication distances are less than a millimeter (and possibly measured in Angstroms), such as in 3D structures (and to a lesser degree within a planar structure), communication power requirements are feather hair faint.

    Please correct any mistakes boldly everyone!
    Jan 20, 2015. 09:24 AM | 5 Likes Like |Link to Comment
  • Slow Train Comin' - Micron, Intel And 3D NAND [View article]
    Fantastic article and subsequent discussion - about as good as it gets in my novice experience, and a scintillating example of superbly civil and constructive human engagement. If only the rest of the world could be so productively tuned...

    I have nothing like as much solid and actionable information or detail to contribute, sorry, but:

    In my estimation Intel has its eye on a critically important longer goal as it maneuvers in the memory and storage technology environment and its relationships with Micron and others: A modern incarnation of the SHGB (Smoking Hairy Golf Ball).

    Whatever performance and economy gains are achieved in memory and storage, overall system performance remains comparatively constrained until all functional system blocks are highly intimate with each other. In my view an SC (System Cube) or Ball (System Ball) is this decade's Holy Grail which must ultimately replace all isolated chip based systems, including multi-chip packages, none of which can compete in performance with TSV (Through Silicon Via) enabled stacked chips as the HMC (Hybrid Memory Cube) so vividly illustrates. As I discuss at (Sorry for the same old reference ad nauseam.)

    The HMC seems to hover continuously but coyly in the background of all other ongoing technology advancement work, almost like a ghost which we only rarely notice even though we know it's there. But I suspect Intel and Micron brass and technologists never lose sight of SC and Ball goals - I suspect they have a very clear understanding of the immense corporate treasures awaiting the victor in the race to that goal, and thus align all other work to remain on an efficient path to that achievement.

    And so far as I can see neither Intel nor Micron could effectively partner with anyone else in pursuit of that goal. That suggests to me that neither will intentionally strain their mutual relationship beyond the most gentle of nudges. I respect that Intel and Micron publicly released nonaligned postures in comments about 3D semiconductor storage fabrication, but suspect it was unintentional, or at most just a slight nudge which is no threat to the productive future of their relationship, and causes no significant discomfort to either firm.

    In these times TSV technology as demonstrated by the HMC seems to me to be the only practical path to a modern incarnation of the SHGB, the SC and Ball, and Intel seems to have attempted (and perhaps still is attempting) to make TSV practical in a production environment. I'm not privy to Micron's recent TSV refinement activity, but speculate that efforts are likely ongoing there too.

    In the meantime we might speculatively connect dots from suspected near vertical etching achievements in 3D storage fabrication to TSV technology - if it's been or will soon be achieved in 3D storage fabrication, maybe the advancement is at least partially applicable to TSV fabrication as well. Granted the etching heights are enormously different - 'near vertical' relative to deposition layers might not be nearly as 'vertical' over the span of the thickness of a die. But neither are TSV dimensions comparable to memory cell dimensions, and thus one must adjust scale to judge 'near vertical' etching performance for the environment in question. In any case, near vertical etching progress in either pursuit might be at least partially relevant to the other. Maybe...

    On another matter, Micron strikes me a stunning bargain right now. In my estimation its price is very low primarily due to derivatives pressures rather than ordinary news and market valuation. Micron is very heavily owned by institutions - evidently currently 90.83%. And a great deal of money was at stake with the derivatives which just expired as was noted at Only 9.17% of its shares are in common hands (including perhaps a significant number of those in our collective hands, leaving even less for ordinary Main Street investors). And most Moms and Pops can't confidently grasp the technical and even industry consolidation details of Micron's story, so they're easily spooked by any skeptical news or views. Those combined factors leave Micron's common price especially susceptible to derivatives pressures and large institutional player market timing logistics in my speculative view, and just drove it down aggressively toward its minimal derivatives reward price - I doubt Micron would be anywhere near $29 per share sans the huge load of derivatives which just expired. It declined over about the month prior to expiration of the big January derivatives load last year too, then ultimately recovered and resumed rising. Maybe that's rather common for a robustly rising security when no substantial news is in the air prior to a big derivatives expiration, I don't know...

    Considering just the ordinary factors, such as Micron's position in industry, its very low P/E (evidently 8.46 for a current year $3.58 EPS estimate), and its average analyst's target price of $41.66, Micron is in my view a terrific investment opportunity right now - we're lucky to have this chance to purchase as many common shares and calls as we can, and to hold our fresh new common from our exercised calls. I suspect that prior to Micron's next quarterly report, which presumably will underscore Micron's new position as a dependable profit making firm, investors will bid Micron back to a more sane price. I also suspect analysts will raise its target price within the next two quarters.

    But first Micron might linger in this cellar for a while as weak hands with margin loan calls, including those who didn't have enough cash or other holdings to fully finance exercise of their Micron calls, are forced to sell some of their common. But my guess is that once that activity's substantially over, Micron's price will steadily and rather rapidly recover.

    From an investor's perspective, this strikes me as a very seductive buying opportunity. For example, though still not dirt cheap, I nonetheless find current January 2017 call prices compelling.

    As usual, intensely concentrated in Micron common and calls, and Intel calls, and now, after exercise of some of those Intel calls, Intel common too. But Micron remains by far my most dominant holding, and I might sell a sliver of my Intel common (even though I think it's a superb holding too) to fund more 2017 Micron calls.

    But of course all investors must steer their own ships...
    Jan 19, 2015. 09:08 PM | 10 Likes Like |Link to Comment
  • Slow Train Comin' - Micron, Intel And 3D NAND [View article]
    Hi Ol' Kiddy,

    Thanks! If inclined, please request:

    1. Current and expected future fabrication practicalities for TSV (Through Silicon Via) utilized in the HMC (Hybrid Memory Cube).

    2. And their opinion about when TSV is expected to appear in other semiconductor products, such as Intel creating an SC (System Cube) or Ball (System Ball).

    I'll add references in another comment below soon. And more is at

    It seems to me that if TSV becomes practical enough for robust production of the HMC, it'll also be quickly adopted in a variety of other complex semiconductor products. The implications strike me as profound. So my guess is that TSV development isn't expected to transition to a cost efficient process in the foreseeable future, or it is, but for competitive reasons Micron and Intel are loath to reveal any details. I have no clue which.

    But my feeling is that efficient TSV fabrication is ultimately inevitable. As are the SC and Ball. So as an investor, I'd love to see someone wink or nod in response to a question about TSV's status or future.

    Thanks bunches!
    Jan 19, 2015. 07:09 PM | 2 Likes Like |Link to Comment
  • Micron: A Big Value Story Most Of The Market Is Missing [View article]
    A genuinely interesting dividend discussion thread - a rarity in my novice experience.

    I feel more comfortable with zero dividend firms - all else equal, they retain more financial flexibility and can thus better nurture growth and resolve problems. In my view dividend centric investors and institutions which cater to them are short sighted or impatient, and trying to appease them even in limited measure weakens strategic options and growth focus. (And as noted magnifies administrative burdens.)

    Declaring a dividend might increase Micron common holding ranks by attracting dividend centric investors, but the cost might be reduced interest by those who seek firms which fully focus on growth of core corporate strengths and income. I'm skeptical of whether there would be any net gain short term, and I suspect there'd be a net loss long term (because robust growth beats dividends for overall investor appeal).

    Ultimately trying to be everything for everyone is folly. To best serve investors, in my view Micron would be wise to simply keep their eyes fully focused on the growth ball and retain maximum corporate flexibility.

    And dispose of the hideously misconceived ('Let's bet lots of money against our own firm.') convertibles as rapidly as practical.

    Steve Jobs' thought dividends unwise. And though numerous complicating factors were at play, Apple's performance under his leadership suggests in at least some small measure that his dividend view was correct.

    Patience. The market will ultimately value Micron reasonably. And that valuation will be highest if Micron simply maintains full focus on its core strengths and growth, and resists chasing any reality disconnecting dreamscapes.

    In my view...

    Very heavily concentrated long Micron common and calls and Intel calls. (And I'd be even more enthusiastic with Intel if they'd taper their dividend to zero. (And Apple too.))
    Dec 22, 2014. 03:37 AM | 2 Likes Like |Link to Comment