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H. Bruce Campbell

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  • Intel: Google Is Not A Threat [View article]
    I suspect English isn't Vivek's native language. Mastering a second language is really tough of course - it's a long and daunting process, especially if begun in middle or late adulthood. It's wise to allow generous margin - mastering English is nothing like easy.

    (And even native English speakers are frequently guilty of truly hideous grammar and word misuse...)
    Dec 15 07:40 PM | 3 Likes Like |Link to Comment
  • Intel: Something Very Big Is Going On [View article]
    It's a compelling concept, thank Russ!

    If Intel calculated that they or, eventually, Samsung could manufacture storage at near enough to hard drive manufacturing costs to make whatever cost difference would exist an insufficient savings to compensate for the many dramatic performance advantages of SSDs, then they were faced with a striking new paradigm: Hard drives would essentially cease to be viable in almost all new products.

    If that was the case, Intel knew someone would capture the new paradigm storage business at a relatively near term transition time. It seems safe to say Intel would prefer that they be the winning firm. And presumably they'd like to win the fast growing and very lucrative storage business dramatically, so that they could dominate it for the foreseeable future.

    And in my estimation TSV will play a very important role in this too.

    Just speculating very wildly, it strikes me as a bit unlikely that the US government would stand in Intel's way. High technology treasures are national treasures with national security implications. If the US government views the matter as a choice between Intel and a foreign firm, in my estimation they'll just wave Intel through the turnstiles.

    Intensely long Micron common and calls, and modestly long Intel calls.
    Nov 15 04:50 AM | 2 Likes Like |Link to Comment
  • Intel/Micron: How IC Packaging Will Drive Them Together [View article]
    Russ: What a superb article! Thanks so much!

    GoRavens: Agreed. In my view TSV ultimately and inevitably delivers profound technical advantages over a very broad range. And thus competitive pressures driving TSV advances, particularly with searing hot fire in their belly Samsung looming over the landscape, are enormous.

    The captains of the primary firms involved can't afford to be timid in planning for a TSV technology driven future. Otherwise Samsung will have them for lunch.

    Though perhaps an initially very difficult business for Apple to try to manage, maybe they feel compelled to consider acquiring Micron very seriously anyway. I doubt Apple wants to live with constant critical component supply logistics nightmares forever. Given their position, they might have to fab their own critical semiconductors to remain genuinely competitive long term.

    In my minority view, at this time the Nippon (Japan) related socio-political realities of Micron's Elpida acquisition are such that Micron must try to be as coy as possible about their earnings for at least the next few months. This creates a fleeting opportunity for either Intel or Apple. So in my view both firms might feel compelled to act as quickly as they reasonably can - to beat the other to the prize, and to acquire it while the appearance of its true value is being intentionally held to an artificially low level.

    Intensely long Micron common and calls.
    Nov 7 08:42 AM | 2 Likes Like |Link to Comment
  • Intel And Apple: An Interesting Tidbit [View article]
    Seculating in a vacuum:

    To me TSV is the lingering elephant in the room. Hypothetically, if TSV's matured enough to be very high yield, cheap, tiny, and supported by existing fab infrastructure, then at some point a meeting took place at Intel, and a similar one at Samsung, wherein someone said, "You know, we can allocate functions to separate die now to substantially reduce individual die size and thus dramatically improve yields, and thus slash cost, with precious little or no loss in performance. We can just stack the die now. The handcuffs are finally off."

    If TSV can be efficiently fabricated now (I don't know whether that's true), then that meeting simply had to have taken place at Intel and Samsung. And Apple and TSMC and anyone else who's paying close attention has to be aware of the situation.

    The finished product OEMs live or die on customer price and margins of course. And Apple and Samsung are in a long and very bloody battle to the death for the phone and tablet markets. All else being very roughly equal, the one with the lowest prices and highest margins will ultimately prevail. TSV enabled small die could be a mighty powerful tool in that struggle...

    It's very hard to judge, but I suspect Apple and Intel are capable of protecting a big secret (as they did years ago when Apple switched from the G series processors to X86). And I like to think Apple's still pretty bright.

    If all that speculation's about right, and on the assumption that Apple will never pump money up Samsung's skirt again, and on the further assumption that Apple saw the TSV future reasonably early, then either TSMC has secretly mastered TSV fabrication, or Russ is right - their deal is with Intel.

    But my view is based upon a conviction that TSV, if it can be efficiently fabricated, is a dramatic game changer.

    Imagine that you and your family, extremely impatient and irritable by nature, but terrified of flying, decide to take your subcompact car on a rode trip from Miami to Seattle. Horrific grueling suffering lies ahead... But fortunately you have the sympathy of some mighty capable and very playful extraterrestrials who seek to test a new toy their species recently developed. It's capable of extracting a section of Earth's crust about a kilo thick and stacking it, fully intact, on top of another section (leaving a little space between for tall geography or buildings, and for air to circulate). So just for grins, and to make your trip much easier, they extract all the American states, then stack them, with Alaska on the bottom, and Rhode Island on the top. And they install lots and lots of pillars between them to support the stack. And each pillar (TSV) is equipped with a few speedy car sized elevators. These are very playful aliens...

    Now you can drive from Miami to Seattle in about an hour. Maybe just 45 minutes. That sure beats 60 hours... And a lot of gas money is saved to boot.

    That's TSV. It changes everything. If it's efficient to fab.

    But I'm speculating in a vacuum - I simply don't know how efficient fabrication of TSV is at this time. It seems odd to me that there's so little chatter about it, suggesting that it's just not efficient enough to fab for prime time yet. Or that everyone knows how big a game changer it is, and thus won't breathe a word about where their firm stands with it until a shipped product tear down reveals it.

    Because of the strong partnership between Intel and Micron, I suspect they're more TSV capable than anyone. I also suspect Intel wants the Apple fab business enough to more than offset discomfort with fabricating ARM based processors, though that's a mighty tough call.

    But hypothetically, Apple might want Intel too, partly because it's not just the CPU and GPU at play of course, but also DRAM. Intel and Micron might be able to efficiently stack the mobile DRAM together with the other die relatively soon too.

    Samsung seems like the only other player who might be able to do that relatively near term. I doubt they're as close to that capability as Intel / Micron, but they're a bloody quick study - they'll probably get there in rather short order.

    In my estimation Apple would very highly prefer to get there first. And Intel / Micron seem to me like their only practical option to achieve that...

    But I'm speculating in a vacuum. And I make many mistakes...

    Intensely long Micron common and calls, modestly long Intel and ChipMOS common and calls.
    Sep 16 08:51 AM | 1 Like Like |Link to Comment
  • Intel And Micron And Depreciated Fabs [View article]
    And many thanks to Russ for alerting all of us to Micron's story so early, and with such compelling credibility. This is a uniquely superb team in my experience, but it all started with Russ. And his energy, enthusiasm, and terrific story telling march on to our great delight.

    May he live in perfect health and happiness until the Universe falls to its absolute zero temperature and maximum entropy heat death (if that is in fact its fate).
    Aug 10 04:30 PM | 2 Likes Like |Link to Comment
  • Intel And Micron And Depreciated Fabs [View article]
    Russ articulated his popular views about this vigorously and in great detail in numerous prior articles. They're terrific reading, still timely, and readily available by clicking on his articles link of course.
    Aug 6 04:11 PM | 2 Likes Like |Link to Comment
  • Intel: OK, Where Are The Apple 'A' Chips Really Going? [View article]
    "And me too of course!" That is, I'd love to hear from you about it too!

    TSV Enabled opportunities seem very exciting to me in general terms. But I don't have any direct monolithic design, fabrication, capex, nor other work experience with such firms. So I could very well miss critical technical problems (though I'm very skeptical that the oft repeated thermal management issue is a genuinely significant hurdle), and I might badly misjudge financial and corporate logistics issues.

    You bring direct experience, analytical skill, and your popular personality to the table, filling in a great many important blanks which I can only vaguely guess about. Almost everyone here has skin in this game, and in my estimation many would like to further explore how TSV might leverage their skin into more skin.

    And I'll bet you've already got a couple of ideas about how to make it clear in the article that it's not just about technology, but skin too...

    May Seeking Alpha judge wisely...
    Jul 17 04:51 PM | Likes Like |Link to Comment
  • Intel: OK, Where Are The Apple 'A' Chips Really Going? [View article]
    Hi Russ,

    No formality necessary for me - Bruce please. And "That was very well done." from Russ Fischer is a very highly prized trophy on my wall, thank you!

    A wall built in substantial measure by funds your experience, insight, exploratory heart, tireless energy, and community team spirit made possible. Again, thank you!

    The profits are very helpful of course. But ultimately the trophy holds the greatest meaning for me.

    Given the unique position Intel and Micron forged together for leveraging this important new technology, and its inherent and very substantial business implications, perhaps Seeking Alpha would approve such an article - maybe they'd perceive that it's intrinsically investment relevant. They certainly should. I'm sure the community here would love to hear from you about it. And me too of course!
    Jul 17 11:26 AM | 3 Likes Like |Link to Comment
  • Intel: OK, Where Are The Apple 'A' Chips Really Going? [View article]
    Just speculating wildly of course:

    Apple strikes me as either possessing a terrific secret rapport and loose partnership with Intel as Apple executes a terrific secret long term plan for a transition to Intel technology, or is simply adrift - at a loss for how to steer their corporate ship into the technical future. (Insofar as mobile products are concerned.)

    Intel possesses a superb but partially coy working relationship with Micron which will enable it to leverage TSV technology to its limits. If TSV and chip stacking prove to be relatively cheap and easy to fabricate, then Intel will be (or is) in a position to reallocate functional SoC blocks plus functions previously relegated to other die, like system RAM, into a very tight knit communities of cubes, in which every cube can communicate with every other cube at very near internal die speed and power levels, or even into a single SC (System Cube).

    At this time firms try to cram as much as possible into an SoC die. That's tough at 32 and 22 nm, and perhaps bloody tough at 14 nm. TSV might remove most of the pressure to put everything into a single SoC die. For example, the GPU might be reallocated to the HMC, making it an HMGC (Hybrid Memory & GPU Cube). The GPU would then be extremely intimate with system RAM, yielding speed and power conservation performance gains. Shared cache might be shared across cubes as well, or, if RAM access speed were sufficient, reduced to very modest size, leaving little more than processor cores on the SoC die. The processor could then be fabricated on a much smaller die, perhaps dramatically improving yields at challenging process nodes such as 14 nm.

    Near die level communication speed and efficiency within and between cubes bestows a great deal of functional block allocation freedom which simply didn't exist before. And that freedom dramatically transforms fabrication logistics, opening entirely new options. Intel might be in a position to allocate functional blocks to separate die with almost no performance loss, thus allowing them far more options to optimize yields at challenging fabrication nodes.

    If TSV can be fabricated efficiently and consumes only modest die real estate, to me the implications are profound. But a partnership with a robust and technically advanced memory firm is critical. Intel possesses that with Micron of course. To me that's huge. So far as I'm aware, no other firm has anything even remotely like such a partnership except Samsung, which has both fabrication technologies in house of course.

    If Apple's not deeply involved in this, they're desperately adrift in my estimation. But Apple would be crazy to allow any hint of such a long term plan to leak to the outside world. And given their history of rather severe angst with Samsung and Google, my guess is that everyone at Apple is thoroughly wedded to a corporate culture of absolute secrecy in such matters - every soul at Apple understands the critical sensitivity of long term core technology plans as the firm tries to protect its innovations from the likes of Samsung and Google. The pressure is especially great because Samsung is in a position to wed processors with HMC if they're technically astute and forward looking enough. So no American firm wants any hint of custom developments in this area (outside the HMC Consortium) to leak to Samsung.

    And Intel knows this too, and thoroughly respects it, as does Apple respect Intel's secrets.

    For many mobile products a single SoC cube incorporating all significant functions - a mini 'Smoking Hairy Golf Ball' of sorts - a single cube of processor cores, GPU, RAM, radios, and perhaps more, might prove to be the highest performance and most die and product fabrication efficient means to implement primary silicon functionality in the product.

    TSV may become (or already is) truly efficient. I suspect that's inevitable because of the dramatic functional block reallocation options it opens, and thus the dramatic die fabrication options it opens, plus the performance gains it enables (especially in RAM access speed and efficiency) for CS's (Cube Systems).

    If Mother Nature isn't blocking this path, in my estimation Intel and Micron are pursuing it extremely aggressively. And with as much secrecy as possible. If Mother Nature is blocking this path with TSV size or fabrication hurdles which are simply too daunting, then precious little of my speculation has any merit. Otherwise it seems to me that we're looking at a cube intensive future. Which Intel and Micron seek to dominate.

    And Apple would be nuts and truly adrift to be on the outside of that evolution. And TMSC and their peers have no Micron like partnership to enable such a future. Samsung is the wild card and sole threat. And needless to say, Apple sure as blazes won't wed with them for any such future.

    That leaves Intel and Micron. To me, the writing's on the wall. Or maybe etched deeply into the wall...

    All just my personal wild speculation of course. Intensively long Micron common and calls.
    Jul 17 08:36 AM | 5 Likes Like |Link to Comment
  • Intel Could Be Hiding Something Huge [View article]
    I disagree with a couple of points in this specific discussion branch. My sense is that the memory wall is a significant performance bottleneck for even relatively pedestrian systems such as tablets and laptops for example.

    However, the overall line of thinking in the discussion makes sense to me. Specifically I thematically agree with Fidgewinkle that "They probably want to take some of the ever increasing cache off of the CPU die to better manage yield.", although I don't necessarily view it as just a yield centric issue.

    Regarding HMC and processor cache design, presumably there are lots of superb analysis of cost / benefit tradeoffs for on chip cache size for each significant type of processor (such as those for phones, tablets, laptops, desk tops, and servers) when the overall product utilizes traditional RAM. It seems to me that HMC slants all those guidelines toward smaller cache sizes, since HMC RAM is much less time distant from the SOC than traditional RAM - less RAM interaction latency suggests a reduced cache size for optimum cost / benefit tradeoffs.

    In the case of modest performance products such as phones, where the HMC is likely to be exceptionally close to the SOC anyway, I'd think the need for on chip cache would be minimal, allowing dedication of much more actual SOC silicon real estate for other functions, or to simply reduce chip size and thus cost. Perhaps rather dramatically so. (But I don't know how size and speed critical the SOC's GPU's memory needs are.)

    Just guessing extremely roughly, maybe there'd be about 2 cm separating the SOC and the HMC in a phone. And while normally I'd assume a practical signal propagation speed of about 17 cm / nS, in the case of a close proximity HMC maybe just half that, about 8 cm / nS, due to unusually high predominance of irregular transmission impedances, since a high proportion of the short distance involved might be mechanically complex and irregular.

    But still, that suggests that HMC is only about 500 pS distant round trip. But add delays for the HMC system itself to manage data flow. But we're still in the very rough neighborhood of just one clock cycle for a 1 GHz processor. And maybe only half that, because the HMC / SOC separation distance might be only 1 cm or even less, and maybe the signal paths can be made relatively clean and thus propagation speed closer to 17 cm / nS.

    So with such quick access to HMC RAM, I wonder whether the cost / benefit of on chip cache falls dramatically to a very modest cache size. Thus freeing a lot of silicon real estate for other functions, or to reduce chip size, and thus fabrication cost.

    I don't know how much real estate Haswell allocates to shared cache, but I'll wild guess 15%. Maybe competitive processors allocate about the same amount.

    If you could eliminate or reallocate most of that real estate yet suffer no overall system performance degradation (or perhaps gain overall performance, including power conservation), and if ARM, Qualcom, et. al. couldn't do that, I'd think you'd simply have a superior product, and capture a lot of extra market share. Good is never good enough after all - everyone wants the best. And ARM, Qualcom, et. al. might find themselves offering only second best, possibly in all three categories - effective speed, power consumption, and fabrication cost. And possibly by significant margins.

    Intel's not a member of the HMC consortium. Whether Micron serves as their proxy might just be a question of semantics. I simply view Intel as disinterested in being captive to the consortium's specs. From their perspective it makes far more competitive sense to, in tight partnership with Micron, and sans any HMC v1.0 specification constraints, develop custom HMC / SOC products for all categories of products, then sell those to OEMs at great competitive advantage compared to ARM, Qualcom, et. al. options.

    I'm a bit suspicious that competitors, perhaps already well behind Intel in incorporating HMC logistics into their processor designs, will as a practical matter be forced to honor the HMC consortium's standard because they won't be able to fund custom HMC design. They don't have anything even remotely like an Intel / Micron partnership, and aren't likely to have anything similar for the foreseeable future.

    If all that's very roughly correct, it implies some very happy days ahead for Intel investors.

    However, I'm just speculating as a general circuit design EE - I don't really know enough about the esoteric details of processor design to feel terribly confident in my appraisal. But we do all know what the speed of light is - there are some immutable facts here. And we also know that Micron and Intel have a very close and effective relationship, and that Intel isn't a member of the HMC consortium.

    And we know that ARM, Qualcom et. al. don't have a Micron like buddy. To me, with HMC nearing implementation (in my estimation), that's huge.

    I still have lots of questions. Technically, I don't know how critical the SOC's GPU's timing to memory is, and thus whether HMC can reasonably meet its needs. That could limit how much cache could reasonably be eliminated.

    And I don't know what the devil Apple, also very conspicuously absent from the HMC consortium, is thinking or doing. But Apple does owe Intel a favor, and is understandably very secretive. So it's only natural to wonder whether Apple and Intel are close but extremely coy development partners on an important project. The TSMC / Apple relationship notwithstanding...
    Jul 11 07:35 AM | 3 Likes Like |Link to Comment
  • Intel Could Be Hiding Something Huge [View article]
    As best I understand the matter, overall system performance is still significantly limited by the memory wall. HMC will breach most of it, but Intel's not a member of the Hybrid Memory Cube consortium, and thus not a party to the recently released Hybrid Memory Cube Specification 1.0. Nor is Apple.

    Considering recent Intel / Micron technology and business partnerships it seems clear that Intel's deeply involved in HMC, but might not implement it in a manner that's compatible to HMC spec 1.0.

    Speculating, perhaps Intel intends to implement HMC in a proprietary manner which is 'ETC' (Extremely Tightly Coupled) with its 14 nm processors, yielding an overall system performance advantage which can't be achieved with HMC spec 1.0. Micron would provide the proprietary HMC per Intel's specs, furthering a trusted partnership which has been very fruitful for both firms.

    Also conspicuously absent from the Hybrid Memory Cube consortium is Apple. Speculating wildly, perhaps Apple, which desperately needs exciting new products, and seeks to build them with non-Samsung components to the extent possible, will be a key customer for Intel's hypothetical 14 nm ETC SOC / HMC products.

    (One press report announced that Apple contracted with TSMC to provide future processors, but it's not yet entirely clear how accurate that report is, or if true, how extensive the supply arrangement is. In my very rough estimation it doesn't preclude an arrangement for future supplies of 14 nm ETC SOC / HMC components from Intel / Micron.)

    I'm just making all this up using ad hoc terminology of course, sans any actual evidence, except that being so conspicuously absent from the Hybrid Memory Cube consortium is, in my view, evidence that something unique involving HMC is likely brewing at Intel. There's zero chance they're ignoring HMC technology. Yet they're not a member of the Hybrid Memory Cube consortium. Technically it makes sense that they could squeeze more performance from an ETC SOC / HMC system when free to design sans any constraints. And their customers might not much care about HMC spec 1.0 or later - if Intel's products significantly outperform competitive options, Intel will make the sale irrespective of whether the product's compliant with an HMC spec.

    Just wild speculation on my part. But I agree that silence sometimes speaks volumes. I guess we'll see rather soon. But I've already placed my financial bets (long Micron and Intel)...
    Jul 8 01:18 AM | 5 Likes Like |Link to Comment
  • Intel: Does The Memory Business Make Sense? [View article]
    I don't know how close TSV and HMC are from practical mass fabrication, but based upon ancillary events my sense is that they're close, or perhaps very nearly ready. Micron hosts an HMC consortium, and I'm almost certain an IEEE HMC standards committee, and their work seems to be well developed. In a hasty search, I found this Micron blog page related to the consortium (there's a rendering of an HMC chatting with a processor embedded in the text too): http://bit.ly/11kOQrC. I presume there's far more direct and thorough material on the Micron site, but time constraints prevent me from a better search at the moment.

    In 2012, at very roughly the time Micron formed the standards committee (or consortium, I'm not certain which, or even if they're essentially the same group), I noted that Samsung was a member, but Apple wasn't. That struck me as quite strange - it certainly can't be an Apple oversight, which to me implies a coy backdoor HMC partnership with Micron, Intel, or both. But not being a member of the committee is bloody conspicuous, so ultimately the situation just baffles me.

    In any case standards develop work seems to me to imply that TSV and HMC are nearing readiness for production. And though this is pure unfounded speculation, I suspect Apple already has prototypes of HMC based end products in its labs, courtesy of Micron (or perhaps Intel) prototype HMC. But any such Apple development work is certainly behind hermetically sealed doors, with no outside clues until sleuths sniff that something's afoot based upon large component orders to outside vendors. If I were Apple I'd place a phantom order for conventional memory to try to cover the actual nature of a new HMC based product. Perhaps Elpida or Micron would receive the order, and file it under "Cover story for Apple's big HMC order".

    Needless to say, I'm just speculating wildly - I don't have any definitive information about TSV or HMC's proximity to prime time production. But my guess is that it's much closer than is occasionally suggested in this discussion.

    Many thanks to RJackson29 and others, and Russ of course! I learn so much here...
    Jun 18 03:21 AM | Likes Like |Link to Comment
  • Intel: Does The Memory Business Make Sense? [View article]
    Scintillating article as usual for Russ!

    Based upon the Wikipedia material at:
    http://bit.ly/17Ohjd2, http://bit.ly/17OhhSD, and http://bit.ly/17OhhSF, the German company Robert Bosch owns the "Bosch Process" patent which leverages DRIE (Deep Reactive Ion Etching) in a process which can create vertical holes through silicon substrates.

    Does anyone know whether this is the foundation process Micron Technology uses to create TSVs? And does anyone have any further patent landscape information such as new patents associated with fabrication refinements of the process, or additions to the process such as making the vias highly conductive, capping and bumping the holes to facilitate efficient connections between stacked chips, or others?

    I vaguely suspect TSVs weren't already in broad use because sufficiently efficient fabrication wasn't previously possible. Just based upon extrapolation of recent events we're all aware of, Micron and Intel's research and development would seem to have refined the process enough to make it practical in their foundries. If so, presumably they've tried to erect the best patent protection possible for their refinements. But I'm just speculating about all this.

    I assume the patent landscape is critical to Micron and Intel's ability to protect and maximize return from their research and development investments in TSV and HMC. So presumably we'd all like to know how strong their patent positions are in these areas. Does anyone have any tangible information about it?

    I posted the same question under my TSV and HMC article. Forgive my duplication please.
    Jun 15 07:06 PM | 4 Likes Like |Link to Comment
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