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Mordechai Rorvig  

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  • Intel: Understanding Multiple Patterning At 14 Nanometers And Below [View article]
    @gigabob_,

    great questions. I wish I could answer them. You're right that mask costs and the relation with the mask industry is a crucial underlying point here, which I didn't address in the article. I'll try to stew over what you're talking about.

    It's not clear how limiting the cost overhead due to multiple patterning will be. If you listen to ASML's last conference call, one maker of EUV technology, CEO Peter Wennink talks about how SAQP and multiple patterning at 7 nm is a "world of pain". Nevertheless, no one says it's impossible, and TSMC and others are actively developing the technology. You may be correct that beyond 7 nm, another technology besides multiple patterning must become the mainstay; but it's not clear to me.
    May 6, 2015. 07:42 PM | Likes Like |Link to Comment
  • Intel: Understanding Multiple Patterning At 14 Nanometers And Below [View article]
    @Alex Cho

    thanks for your comment and encouragement. I am coming from the other side, with more of a physics background, trying to learn more about financial analysis. I am encouraged to here that there is an audience for deeper technological analysis on SA. I think you're right, that with collaboration between different backgrounds, we can ultimately approach the most well informed picture for everyone.
    May 6, 2015. 07:29 PM | 1 Like Like |Link to Comment
  • Intel: Understanding Multiple Patterning At 14 Nanometers And Below [View article]
    @Vlad Hristov,

    Glad I could contribute a piece of scientific justification to your argument.

    If I recall correctly, this discussion was particularly prominent in the industry in 2012, 2013. There are arguments on both sides. The fabless model has shown it can work; TSM, for example, has grown 24% in the past year on expanding revenues. To some extent, the fabless model has to work, because fab capex requirements are so high that most companies have no choice to develop their own.

    Maybe the main obstacle to your thesis (only two semi manufacturers, INTC + SAMS) is that it would require either (1) tons of those other competitors to go out of business, or (2) an enormous amount of industry consolidation. But the first route will be extremely difficult, due to the tenacious competition of the industry. The second route would seem to be difficult because the tech industry has historically not shown that much consolidation.

    How would you envision your scenario materializing, and in what timeframe?
    May 4, 2015. 10:02 PM | Likes Like |Link to Comment
  • Intel: Understanding Multiple Patterning At 14 Nanometers And Below [View article]
    @William Tidwell,

    thanks for the feedback. I agree it would be very interesting to know what's going on behind the scenes for Apple in regards to this evolution.
    May 3, 2015. 11:14 PM | Likes Like |Link to Comment
  • Intel: Understanding Multiple Patterning At 14 Nanometers And Below [View article]
    @frmrVZguy,

    I am not familiar with what you're discussing, but I would be interested to hear more about it. Thank you for your thoughts.
    May 3, 2015. 11:12 PM | Likes Like |Link to Comment
  • Intel: Understanding Multiple Patterning At 14 Nanometers And Below [View article]
    @oak8292,

    thanks for pulling out those quotes from Chris Mack related to multiple patterning. I have looked at his writings and commentary and found them helpful as well. I think his point about investors at conferences perhaps neglects to consider the fact that an investor can and should also be, at least hypothetically for example, a working scientist themselves.
    May 3, 2015. 11:11 PM | Likes Like |Link to Comment
  • Intel: Understanding Multiple Patterning At 14 Nanometers And Below [View article]
    @Bruce Burnworth,

    good point about trade secrets.

    I agree with you that your sentence in question could have been phrased better. Let me paraphrase my idea another way: Due to process complexity, integrated circuit designs will tend to become more similar, due to layout restrictions. However, individual transistors and transistor sizes from each manufacturer (at comparable nodes) will tend to look more different, because there is more and more 'secret sauce'.

    On the other hand, one could argue transistors may start to look more similar, since the extreme dimensions require greater adhesion to a theoretical ideal. I admit this is a bit speculative.
    May 3, 2015. 11:08 PM | 3 Likes Like |Link to Comment
  • Intel: Understanding Multiple Patterning At 14 Nanometers And Below [View article]
    @David Muncier,

    please feel free to help direct me to more source material, and I will try to incorporate it into my future analyses where appropriate. Specific links or references are most helpful.
    May 3, 2015. 11:00 PM | 2 Likes Like |Link to Comment
  • Intel: Understanding Multiple Patterning At 14 Nanometers And Below [View article]
    @Rudester,

    yes, the question of the relation between product sophistication and business valuation is an interesting and often counterintuitive one. I personally find it a little bizarre how companies like Intel are valued similarly to companies that make burgers or ketchup.
    May 3, 2015. 10:58 PM | 5 Likes Like |Link to Comment
  • Intel: Understanding Multiple Patterning At 14 Nanometers And Below [View article]
    @djrryan,

    thanks for your feedback. The distinction is a little subtle. 10 nm and 14 nm are printed using optical wavelengths of 193 nm; however, the features are themselves much smaller than the optical wavelength. I would also note to be careful to remember the 10 nm and 14 nm node designations do not refer to the actual dimension; the dimensions e.g. for 22 nm and 14 nm nodes are listed in the article, and are larger by a factor of 2-5.
    May 3, 2015. 10:55 PM | Likes Like |Link to Comment
  • Intel: Understanding Multiple Patterning At 14 Nanometers And Below [View article]
    @archae86,

    yeah, I probably should've mentioned that my last two articles before this one were all about ASML, and its participation in and development of EUV technology. You can find them here: http://seekingalpha.co..., http://seekingalpha.co....

    Your question about the competitiveness of EUV versus optical is spot-on and widely discussed within analyst and industry circles. You can see more commentary on this at Nikon's eReview, http://bit.ly/1IEg69l.
    May 3, 2015. 10:50 PM | 2 Likes Like |Link to Comment
  • Intel: Understanding Multiple Patterning At 14 Nanometers And Below [View article]
    @bobcatone,

    more advanced lithography is always necessary every new generation and even in existing generations. If you mean to ask how much lower circuit sizes can go within the paradigm of current advances, then circuit sizes are ultimately only limited by fundamental physical limits, like atomic widths, etc. Sub-optical resolution in theory should be able to go to much lower circuit sizes on its own, using techniques like self-aligned octuple patterning.
    May 3, 2015. 10:44 PM | 1 Like Like |Link to Comment
  • Intel: Understanding Multiple Patterning At 14 Nanometers And Below [View article]
    @techy46,

    always great to hear from people who have been involved in the industry. I'm very happy that you found the article relevant and interesting. I guess there's probably tons of topics like multiple patterning that don't get the attention they deserve. It's hard to connect them directly to the financial case, and I think that makes them difficult to approach on a website like Seeking Alpha. Hopefully, if these articles continue to be well received, I can keep making progress writing about these topics.
    May 3, 2015. 10:40 PM | Likes Like |Link to Comment
  • Intel: Understanding Multiple Patterning At 14 Nanometers And Below [View article]
    @Just Some Guy,

    well, I'm thankful the editors published it anyways, as I like reading about technology and do find it relevant to deeper investing analyses.
    May 3, 2015. 10:36 PM | 1 Like Like |Link to Comment
  • Intel: Understanding Multiple Patterning At 14 Nanometers And Below [View article]
    @CandleFlight,

    thank you for your appreciation. As far as the next big challenge, that's a hard question, I guess; it seems there are many. I know some journalists and scientists have written about carbon nanotubes or nanowires being the next primary transistor technology, after FinFets. That will take much work. I would enjoy researching that topic for a future article, and am glad to know there may be interest.
    May 3, 2015. 10:35 PM | 1 Like Like |Link to Comment
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