Intel, others slow migration to 450mm chip wafers

Lithography equipment giant ASML has "paused" the development of hardware meant to work with next-gen 450mm wafers, which offer 125% more wafer space (and thus better economies of scale) than current-gen 300mm wafers. Likewise, Applied Materials (AMAT) CEO Gary Dickerson says the 450mm migration "has definitely been pushed out from a timing standpoint."

Due to ASML's move, Intel (INTC), which agreed in 2012 to pour $4.1B into the company to help finance investments in 450mm wafers and EUV lithography, has "adjusted" the pace of its payments to ASML.

Last year, Intel began constructing a $2B Oregon development fab meant to be its first 450mm facility. But it's reevaluating its timetable amid soft PC demand and concerns about its share of the bill. Spokesman Chuck Mulloy: "We still believe 450 is the right thing to do ... But we have been clear: we will not do it ourselves."

EUV, considered necessary to maintain Moore's Law long-term, has also seen delays. ASML CEO Peter Wennink recently predicted EUV will reach the stability levels required by chip manufacturers by the 2H16 or 2017.

Other chip equipment makers: KLAC, LRCX, RTEC, NVMI, UTEK, TOELF

Comments (6)
  • markitos
    , contributor
    Comments (207) | Send Message
    That is not a surprise to anyone in the semiconductor equipment manufacturing sector. Besides Intel, no other company wants to spent money to move to 450 mm wafers. I stated that fact numerous times in my SA posts.
    13 Mar 2014, 06:51 PM Reply Like
  • MorrisSean
    , contributor
    Comments (103) | Send Message
    Which products will this effect? From the article it sounded like desktop chips, but I thought they were committed to bringing new tech to mobile first... seems like Intel looses a competitive advantage with regards to cost in the ultra competitive mobile space. Also, if this results in lower margins, Intel may become less aggressive going after market share for tablets. Short turn this news probably doesn't matter (except lowering CapEx) but the road map 2 years out could be a problem.
    13 Mar 2014, 07:20 PM Reply Like
  • markitos
    , contributor
    Comments (207) | Send Message
    Please relax! Delay will not affect any current or future product. Large wafers are useful only for increasing number of dies (chips) manufactured per wafer. Intel does not loose a competitive advantage to no one and I can assure you that Intel will be the first to move to 450 mm wafers when the time is right. In my opinion Intel has declared a total war on its competition and regardless of move to 450 mm now or 10 years later their chances for success are extremely good.
    14 Mar 2014, 01:29 AM Reply Like
  • Jeach!
    , contributor
    Comments (896) | Send Message
    Well, well, that is surely no surprise! Was I right or was I right?


    This is only a start too... more 450 mm delays coming your way, all gift wrapped in "its because of the economy" excuses for those loving Intel fans.


    "ASML CEO Peter Wennink recently predicted EUV will reach the stability levels required by chip manufacturers by the 2H16 or 2017."


    Yep, and how long have they been working on this? And this guy suddenly is able to predict within two quarters, two years off, that it will be "stable".


    Gotta love this FUD.
    13 Mar 2014, 09:07 PM Reply Like
  • Cincinnatus
    , contributor
    Comments (6187) | Send Message
    If you didn't have a knee-jerk reaction to anything Intel you'd view this as negative for Intel's competition. I think it says two things. (a) Intel is likely to have a huge lead when they do transition, and (b) the foundries are so overwhelmed just trying to get to the 20nm and below process nodes that they are unwilling and likely unable to devote money or resources to 450nm wafer development.
    15 Mar 2014, 12:17 PM Reply Like
  • AJFoyt
    , contributor
    Comments (4) | Send Message
    Take a look at a recent post on Semiwiki. EUV is no where near ready. 8 wafers per hour throughput vs 200 Wafers per hour at 193nm. Currently double patterning at 20nm node could go to 5-7 patterns at $75M per cell vs $150M or more for EUV. 450mm for 2.25x the die per wafer will happen. Both are not tied. The biggest issue is defect density. It's a killer now. Gets exponentially worse at each process shrink. Intel even with Trigate technology is struggling at 300mm. Additionally the critical dimension and sidewall roughness at 20nm feature size must be ~.2nm for things to be in spec. Hold that across the wafer means alignments, registration and Post exposure bake on the tracks plus the exposure uniformity must be very very good. Intel's advantage is fab capacity and stringent copy exactly procedures across 7 300mm wafer fabs around the world. No one can match their capacity. This is simple really. They are the only ones running true 20nm front and back end feature size. There is plenty of time to optimize yields before moving to 14nm or 10nm. No need to add 450mm capacity until 300mm plays out. Both F42 in Phx and D1X in Oregon can run 300mm wafers and be converted to 450mm later. Intel was the first to deploy a modular clean room strategy way back in Albq. In F9.1,9.2.... Etc back in the 80's. They have the best gross margins in the industry and need to watch them carefully as they move into the mobile space. Give em' a break; they are not stupid folks.
    13 Mar 2014, 09:37 PM Reply Like
DJIA (DIA) S&P 500 (SPY)
ETF Screener: Search and filter by asset class, strategy, theme, performance, yield, and much more
ETF Performance: View ETF performance across key asset classes and investing themes
ETF Investing Guide: Learn how to build and manage a well-diversified, low cost ETF portfolio
ETF Selector: An explanation of how to select and use ETFs