Lam Research Corporation is a leading supplier of wafer fabrication equipment and services to the worldwide semiconductor industry. For more than twenty five years, our wafer fabrication equipment, services, and extensive technical expertise have contributed to advancing semiconductor manufacturing and producing some of the world’s most advanced semiconductor devices. We are recognized as the market share leader in plasma etch and as a provider of innovative solutions in single-wafer clean.
We design, manufacture, market, and service semiconductor processing equipment used in the fabrication of integrated circuits. Semiconductor wafers are subjected to a complex series of process and preparation steps that result in the simultaneous creation of many individual integrated circuits. We leverage our expertise in these areas to develop integrated processing solutions which typically benefit our customers through reduced cost, lower defect rates, enhanced yields, or faster processing time. Many of the technical advances that we introduce in our newest products are also available as upgrades to our installed base of equipment, a benefit that can provide customers with a cost-effective strategy for extending the performance and capabilities of their existing wafer fabrication lines.
Our innovative etch and clean technologies enable customers to build some of the world’s highest-performing integrated circuits. Our etch systems shape the microscopic conductive and dielectric layers into circuits that define a chip’s final use and function. Our broad portfolio of single-wafer clean technologies allows our customers to implement customized yield-enhancing solutions. With each new technology node, additional requirements and challenges drive the need for advanced manufacturing solutions. We strive to consistently deliver these advanced capabilities with cost-effective production performance, as we understand the close relationship between customer trust and the timely delivery of new solutions that leads to shared success with our customers.
Incorporated in 1980, Lam Research is headquartered in Fremont, California, and maintains a network of facilities throughout the United States, Japan, Europe, and Asia Pacific in order to meet the needs of our global customer base.
Additional information about Lam Research is available on our web site at http://www.lamresearch.com.
Our Annual Report on Form 10-K, Quarterly Reports on Forms 10-Q, Current Reports on Form 8-K, and any amendments to those reports are available on our website as soon as reasonably practicable after we filed them with or furnish them to the Securities and Exchange Commission (“SEC”), and are also available online at the SEC’s web site at http://www.sec.gov.
Etch processes, which are repeated numerous times during the wafer fabrication cycle, are required to manufacture every type of semiconductor device produced today. Our etch products selectively remove portions of various films from the wafer in the creation of semiconductor devices by utilizing various plasma-based technologies to create critical device features at current and future technology nodes. Plasma consists of charged and neutral particles that react with exposed portions of the wafer surface to remove dielectric or conductive materials and produce the finely delineated features and patterns of an integrated circuit.
For dielectric etch, new materials integration often requires etching multi-layer film stacks. In addition to the challenges introduced by new materials and scaling, device manufacturers’ desire to reduce overall cost per wafer has placed an increased emphasis on the ability to etch multiple films in the same chamber (in situ).
Production-proven in high-volume manufacturing for nearly 15 years, our patented Dual Frequency Confined™ technology has been extended to incorporate multi-frequency power with a physically confined plasma. The application of power at different frequencies provides enhanced process flexibility and allows different materials to be etched in the same chamber. Physical confinement of the plasma to an area directly above the wafer minimizes chemical interaction with the chamber walls, eliminating potential polymer build-up that could lead to defects on the wafer. Confinement also enables our proprietary in situ Waferless Autoclean™ technology to clean chamber components after each wafer has been etched. Used together, multi-frequency and WAC™ technologies provide a consistent process environment for every wafer, preventing process drift and ensuring repeatable process results wafer-to-wafer and chamber-to-chamber.
2300® Exelan® Flex™, 2300® Exelan® Flex45™, 2300® Flex™ D Series Dielectric Etch Systems
Our 2300 Flex dielectric etch product family represents a continuous evolution of the productivity and performance benefits of DFC technology. The 2300 Flex family allows a single chamber design to meet the requirements of a wide range of applications through multiple technology generations. Advances in system design, such as multiple frequencies, higher power capabilities and tunable wafer temperature, meet the more demanding uniformity and profile requirements for applications at the 32 nm node and beyond.
As the semiconductor industry continues to shrink critical feature sizes and improve device performance, a variety of new etch challenges have emerged. For conductor etch, these challenges include processing smaller features, new materials, and new transistor structures on the wafer. Due to decreasing feature sizes, the etch process can now require atomic-level control across a 300 mm wafer. The incorporation of new metal gates and high-k dielectric materials in the device stack requires advanced multi-film etching capability. Furthermore, the adoption of double patterning techniques to address lithography challenges at the 45 nm node and beyond is driving the etch process to define the feature on the wafer as well as to transfer the pattern into the film. All of these challenges require today’s conductor etch systems to provide advanced capabilities, while still providing high productivity.
Introduced in 1992, our Transformer Coupled Plasma™ technology continues to provide leading-edge capability for advanced conductor etch applications at the 32 nm node and beyond. By efficiently coupling radio frequency (“RF”) power into plasma at low pressures, the TCP technology provides capability to etch nanoscale features into silicon and metal films. The advanced TCP source design ensures a uniform, high-density plasma across the wafer, without requiring magnetic enhancements that could cause device damage. With a wide process window over a range of power, chemistry, and pressure combinations, TCP technology provides the flexibility required to perform multiple etch steps in the same chamber.
2300® Versys® Kiyo®, 2300® Versys® Kiyo45™, 2300® Kiyo® C Series, 2300® Versys® Metal, 2300® Versys® Metal45™ Conductor Etch Systems
Now in its third generation, the 2300 Kiyo product family combines iterative advances in technology to provide critical dimension (“CD”) uniformity and productivity for a wide range of conductor etch applications. The 2300 Versys Metal product family leverages Lam’s proprietary TCP technology to provide a flexible platform for back-end-of-line metal etch processes. Our etch products perform production-proven in situ etch of complex features. In addition, proprietary pre-coat and post-etch chamber clean techniques provide the same environment for superior repeatability, as well as high uptime and yield wafer after wafer.
MEMS and Deep Silicon Etch
Micro-electromechanical systems (“MEMS”) devices are increasingly being used in consumer applications, such as ink jet printer heads and inertial sensors. This is driving a number of MEMS applications to transition into high-volume manufacturing, which requires the high levels of cost-effective production typically seen in commodity semiconductor memory devices. To achieve high yield in mass production, the MEMS etch process requires wafer-to-wafer repeatability.
TCP® 9400DSiE™ Deep Silicon Etch System
The TCP 9400DSiE system is based on our production-proven TCP 9400 silicon etch series. The system’s patented high-density TCP plasma source provides a configuration to meet the challenges of silicon deep reactive ion etch (“DRIE”), offering broad process capability and flexibility for a wide range of MEMS, advanced packaging, and power semiconductor applications. Incorporation of our proprietary in situ chamber cleaning technology provides etch rate stability.
Three-Dimensional Integrated Circuit Etch
The semiconductor industry is developing advanced, three-dimensional integrated circuits (“3-D ICs”) using through-silicon vias (“TSVs”) to provide interconnect capability for die-to-die and wafer-to-wafer stacking. In addition to a reduced form factor, 3-D ICs can enhance device performance through increased speed and decreased power consumption. Manufacturers are currently considering a wide variety of 3-D integration schemes that present an equally broad range of TSV etch requirements. Plasma etch technology, which has been used extensively for deep silicon etching in memory devices and MEMS production, is well suited for TSV creation.
2300® Syndion® Through-Silicon Via Etch System
The 2300 Syndion etch system is based on our patented TCP technology and the production-proven 2300 Versys Kiyo conductor etch system. The Syndion system can etch multiple film stacks in the same chamber, including silicon, dielectric, and conducting materials, thereby addressing multiple TSV etch requirements.
The manufacture of semiconductor devices involves a series of processes such as etch, deposition, and implantation, which leave particles and residues on the surface of the wafer. The wafer must generally be cleaned after these steps to remove particles and residues that could adversely impact the processes that immediate follow them and degrade device performance. Common wafer cleaning steps include post-etch and post-strip cleans and pre-diffusion and pre-deposition cleans, among others.
Specific challenges at the 45 nm node and beyond include efficient particle and residue removal while minimizing substrate material loss, protecting structures with fragile new materials and smaller feature sizes, and efficient drying. In addition, management of potential defect sources at the wafer edge becomes increasingly challenging as new materials are introduced in the process flow.
Single-Wafer Wet Clean
As device geometries shrink and new materials are introduced, device flows become more complex and the number of wafer cleaning steps increases. The need to increase overall clean efficiency and clean fragile structures without causing damage are reasons why chipmakers are turning to single-wafer wet clean processing technology for next-generation devices.
Over the past decade, a transition from batch to single-wafer processing has occurred for back-end-of-line wet clean applications and a similar migration for front-end-of-line wet clean applications appears to be occurring as the need for higher particle removal efficiency without device structure damage becomes more critical. Single-wafer wet processing is particularly advantageous for those applications where improved defect performance (removing particles without damaging the wafer pattern) or enhanced selectivity and CD control can improve yield.
Single-Wafer Spin Clean Products: SP Series, Da Vinci®, DV-Prime™
With the acquisition of SEZ Holding AG (“SEZ”) in March 2008, we have expanded our portfolio to include single-wafer spin systems, in addition to gaining more than 20 years of experience in clean technology and a substantial installed customer base. This single-wafer SEZ® spin technology for cleaning and removing films has assisted the industry transition from batch to single-wafer wet processing. By offering advanced dilute chemistry and solvent solutions in our systems, our single-wafer spin clean systems address certain defectivity and material integrity requirements.
Single-Wafer Linear Clean Product: 2300® Serene™
To meet the challenges of smaller critical dimensions, increasing aspect ratios, and new materials integration, our 2300 Serene wet clean system is targeted at applications requiring high-selectivity residue removal without damaging sensitive device structures. The system’s C3™ (Confined Chemical Cleaning™) technology combines linear wafer motion with chemically-driven single-wafer cleaning to remove residues with chemical exposure times as short as a few seconds. The cleaning exposure time is optimized for efficient removal of the target materials, while limiting the impact on critical materials. This technology addresses applications that require high-selectivity cleaning, such as high-k metal gate post-etch clean.
Plasma-Based Bevel Clean
Semiconductor manufacturers are paying increasing attention to the wafer edge as a source of yield limiting defects. New materials like porous low-k and organic films often do not adhere as well as traditional silicon or polymer-based films and have the potential to be significant defect sources. By including cleaning steps that target the bevel region, the number of good die at the wafer’s edge can be increased to maximize yield.
2300® Coronus™ Plasma-Based Bevel Clean System
The 2300 Coronus plasma-based bevel clean system incorporates plasma technology to remove yield limiting defect sources. The system combines the ability of plasma to selectively remove a wide variety of materials with a proprietary confinement technology that protects the die area. Incorporating our Dynamic Alignment technology on the production-proven 2300 platform, the Coronus system provides highly accurate wafer placement for reproducible results and superior encroachment control and is designed to remove a wide range of material types, in multiple applications, throughout the manufacturing process flow.
The Lam Research logo, Lam Research, and all product and service names used herein are either registered trademarks or trademarks of Lam Research Corporation in the United States and/or other countries. All other marks mentioned herein are the property of their respective holders.
Research and Development
The market for semiconductor capital equipment is characterized by rapid technological change and product innovation. Our ability to obtain and maintain our competitive advantage depends in part on our continued and timely development of new products and enhancements to existing products. Accordingly, we devote a significant portion of our personnel and financial resources to R&D programs and seek to maintain close and responsive relationships with our customers and suppliers.
Our R&D expenses during fiscal years 2009, 2008, and 2007 were $288.3 million, $323.8 million, and $285.3 million, respectively. The majority of R&D spending is targeted at etch and plasma-based technology applications, with an increasing proportion focused on adjacent markets including single-wafer clean and pre- and post-etch step opportunities. We believe current challenges for customers in the pre- and post-etch applications present opportunities for us.
We expect to continue to make substantial investments in R&D to meet our customers’ product needs, support our growth strategy, and enhance our competitive position.
Marketing, Sales, and Service
Our marketing, sales, and service efforts are focused on building long-term relationships with our customers and targeting product and service solutions designed to meet their needs. These efforts are supported by a team of product marketing and sales professionals as well as equipment and process engineers who work closely with individual customers to develop solutions for their wafer processing needs. We maintain ongoing service relationships with our customers and have an extensive network of service engineers in place throughout the United States, Europe, Taiwan, Korea, Japan, and Asia Pacific. We believe that comprehensive support programs and close working relationships with customers are essential to maintaining high customer satisfaction and our competitiveness in the marketplace.
We offer standard warranties for our systems that generally run for a period of 12 months from system acceptance. The warranty provides that systems shall be free from defects in material and workmanship and conform to agreed-upon specifications. The warranty is limited to repair of the defect or replacement with new or like-new equivalent goods and is valid when the buyer provides prompt notification within the warranty period of the claimed defect or non-conformity and also makes the items available for inspection and repair. We also offer extended warranty packages to our customers to purchase as desired.