Synopsys, Inc. is a world leader in electronic design automation (EDA) software and related services for semiconductor design companies. We deliver technology-leading semiconductor design and verification software platforms and integrated circuit (IC) manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). In addition, we provide intellectual property (IP), system-level design hardware and software products, and design services to simplify the design process and accelerate time-to-market for our customers. Finally, we provide software and services that help customers prepare and optimize their designs for manufacturing.
We incorporated in 1986 in North Carolina and reincorporated in Delaware in 1987. Our headquarters are located at 700 East Middlefield Road, Mountain View, California 94043, and our telephone number there is (650) 584-5000. We have more than 60 offices worldwide.
Combined, these advances in semiconductor technology have enabled the development of lower-cost, higher-performance computers, wireless communications networks, hand held devices, internet routers and a wealth of other electronic devices. Each advance, however, has introduced new challenges for all participants in semiconductor production, from designers and manufacturers to equipment manufacturers and EDA software suppliers, such as Synopsys.
These technological challenges have been accompanied by significant business challenges, increased globalization leading customers to source their products in lower-cost areas, and consumer demand for cheaper and more advanced products.
We believe Synopsys is well positioned to help our customers meet these multi-faceted challenges. We have a broad portfolio of solutions that are highly integrated to solve our customers’ most advanced technological problems. We have a large number of global service and support engineers that help our customers complete their chip designs. We believe our combination of advanced technology and global scale, along with our solid business execution, gives us a competitive advantage.
The IC Design Process
EDA software enables designers to create complex semiconductors. In simplified form, the IC design process consists of the steps described below.
System Design. The first step in a typical IC Design is determining the features and specifications of the chip, its overall architecture, and the division of device functionality between hardware and software. Once the architecture is created and the division between hardware and software made, software engineers develop the embedded software applications that drive an increasing proportion of the device functionality, while the chip designers develop the functionality and configuration of the semiconductor itself.
Register Transfer Level (RTL) Design. RTL design is the process of capturing the intended design functionality created at the system level using a specialized high level computer language, typically SystemVerilog, Verilog or VHDL. Logic Design. Logic design, or “synthesis,” programs convert the RTL code into a logical diagram of the chip, and produce a data file known as a netlist describing the various groups of transistors, or gates, to be built on the chip.
Functional Verification. At the RTL level of IC design, the designer uses functional verification tools such as RTL simulators and testbench automation and other verification tools to verify that the design will function as intended. The increasing size and complexity of today’s ICs and SoCs have vastly increased the time and effort required to verify chip designs, with verification estimated to consume 60% to 70% of total design time. As a result, designers are demanding solutions that can handle increasing complexity at ever higher speeds, and that can reduce verification risk (i.e., find design bugs before designs are taken into production).
Rapid Prototyping. Rapid prototyping is a form of functional verification that uses hardware to accelerate verification in order to accommodate these significant demands. It is also used to accelerate the development of embedded software by software engineers by essentially providing a “prototype” of the chip well before the chip is completed—allowing software development to begin many months earlier than would otherwise be the case.
Physical Design. In the physical design stage, the designer plans the physical location of all of the transistors and each of the wires connecting them with “place and route” products. The designer first determines the location on the chip die for each block of the chip, as well as the location for each transistor within each block, a process known as “placement.” In many designs, placement is performed in conjunction with logic synthesis, a process known as “physical synthesis.” After placement the designer adds the connections between the transistors, a process known as “routing.” With increasing gate counts and design complexity, seamless correlation among physical design and other tools is becoming increasingly important.
Physical Verification. Before sending the chip design files to a manufacturer for fabrication, the designer must perform a series of further verification steps, checking to make sure that the final design complies with the specific requirements of the fabrication facility that will manufacture the chip.
Manufacturing. The design is then translated to a series of photomasks, or physical representations of the design. IC manufacturers use photomasks to produce the silicon wafer containing individual ICs. As IC wire or “feature” sizes shrink, this translation is becoming more and more difficult. These challenges are exacerbated because in advanced designs the feature widths can be smaller than the wavelength of the light used in the manufacturing process, requiring advanced software tools and techniques such as optical proximity correction to alter the mask to ensure the desired features can still be produced. Technology computer-aided design, or TCAD, tools are also used to model individual features or “devices” within the design to help ensure manufacturability. Finally, various yield enhancement tools and technologies are employed at this stage to increase the number of usable ICs contained on each silicon wafer.
Intellectual Property Reuse. As IC designs continue to grow in size and complexity, designers have found that inserting pre-designed and pre-verified design blocks into the design can be an effective way to help reduce overall design cost and cycle time by reducing the number of chip elements that must be designed and comprehensively verified. Usually, such IP blocks represent functions that can be used in multiple applications and ICs, including microprocessors, digital signal processors, or connectivity IP that support such protocols as USB, PCI Express or Ethernet.
Products and Services
Our products and services are divided into five common groupings: Galaxy™ Design Platform and Discovery™ Verification Platform (which are typically sold and reported together as Core EDA), Intellectual Property (IP) and System-Level Solutions, Manufacturing Solutions, and Professional Services.
Galaxy Design Platform
Our Galaxy Design Platform provides our customers with a single, integrated IC design solution which includes industry-leading individual products and which incorporates common libraries and consistent timing, delay calculation and constraints throughout the design process. The platform allows designers the flexibility to integrate internally developed and third-party tools. With this advanced functionality, common foundation and flexibility, our Galaxy Design Platform helps reduce design times, decrease integration costs and minimize the risks inherent in advanced, complex IC designs. Our solutions span both digital and analog/mixed-signal designs.
Discovery Verification Platform
Our Discovery Verification Platform is an integrated and comprehensive portfolio of functional, analog/mixed-signal, formal and low-power verification solutions. The platform includes our simulation and verification products and design-for-verification methodologies, and provides a consistent control environment to help significantly improve the speed, breadth and accuracy of our customers’ verification efforts. The Discovery Verification Platform’s components support industry standards and span both digital and analog/mixed-signal designs.
Intellectual Property (IP) and System-Level Solutions
Synopsys’ IP portfolio includes our IP products and components. Responding to the portfolio demands of designers seeking solutions to reduce their design risk and time-to-market, Synopsys offers a broad portfolio of silicon-proven digital, PHY, analog and verification IP for SoC designs. We provide connectivity IP solutions for widely used protocols such as USB, PCI Express, DDR, SATA, HDMI, Ethernet and MIPI. Our analog IP solutions include analog-to-digital converters, digital-to-analog converters, audio codecs, video analog front ends and touch screen controllers. In addition, we offer SystemC transaction-level models to build virtual platforms for rapid, pre-silicon development of software.
Synopsys’ System-Level Solutions enable customers to, among other things, accelerate verification and embedded software development. The portfolio of system-level products enable chip designers to bridge the gap from system design to implementation. Products include virtual platforms that are fully functional software models of embedded systems, enabling pre-silicon software development and software-driven system validation, solutions for developing, running and debugging virtual platforms, and a rapid prototyping system that accelerates functional verification of large designs and can be used to accelerate development of embedded software on devices, thereby speeding a customer’s time to market.