Freescale Semiconductor's Management Hosts OpenSystems Media E-cast Conference (Transcript)

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Freescale Semiconductor Inc. (NYSE:FSL) OpenSystems Media E-cast Seminar February 21, 2013 2:00 PM ET


Jim Turley

Toby Foster

Robert Redfield

Jim Turley

Good afternoon and good morning, everybody, and welcome to the OpenSystems Media E-cast. Today's topic is on high-performance computing brought to us by the nice folks at Freescale Semiconductor and Green Hills Software. Our speakers today are Toby from Freescale and Robert Redfield from Green Hills. We'll be talking a little bit more about them in just a minute.

But first, more about me. My name is Jim Turley. I'll be the moderator for the seminar today. I'll be introducing our speakers and then at the end of the show, I'll be handling the Q&A from you, our audience.

As we said, today's topic is on high-performance computing, specifically high-performance computing as it relates to network and communications. This is the kind of thing we wouldn't have seen too many years ago. The technology we're about to discuss would have made a pretty darn nice computer or video game console or other high-end machine not that long ago, and now we're embedding it inside communications devices where most of us are never going to see it. That's pretty impressive, especially when we start to get into the details of the device on the software that runs on.

Here to tell us about it, we've got a couple of specialists, again, as I've said, Toby Foster from Freescale and Robert Redfield from Green Hills. Toby is exquisitely well-suited to talk about this topic because he is the Product Marketing Manager for Freescale's Digital Networking Group, which sounds like it's just the right fit for this product. He focuses on the development of high-performance Power Architecture multicore processors. That's what most of us would've called PowerPC not too long ago in Freescale's QorIQ communications processor portfolio. Previous to this, he had roles as a system architect and as an applications engineering manager also at Freescale with the network processors. He's got a Masters and a Bachelors in Electrical Engineering from Harvey Mudd Co, Pomona.

Later on, we'll here form Robert Redfield. He's at Green Hills in Santa Barbara, California. That's what? A couple of hours away from Pomona, I think. He's the Director of Partner Business Development at Green Hills Software, where he creates and manages collaborative engineering, marketing and co-selling activities with the strategic embedded semiconductor manufacturers and related associations. There at Green Hills, he focuses on defining hardware, software product road maps with their partners, with field sales and with early technology sharing initiatives. Sounds like both guys are staying pretty busy.

Before we launch into the good stuff, I've got a couple of notes for you, our audience. Our talk today runs for an hour, and if you haven't done this before, it's pretty straightforward. You get to sit back, relax and watch the slides. Actually, no. We don't want you to sit back and relax. We want you to lean forward and participate. As our speakers are going on here, you have an opportunity to send a shout out to ask questions that we will be asking at the end of the Q&A period.

If you look at your software console there, you'll see that you've got some blue buttons on the screen. Those are pretty straightforward, but I'll walk you through them anyway. Probably, most important is at the lower left corner of your screen. You've got a box that says ask a question, and a blue submit question button right under it. That's where you, our audience members, get to play with our speakers. Type in your question here at any time starting from now right until the end of the talk, type in your question and during the Q&A session, we'll try to get to that and you can ask your question of the audience member. So don't forget to keep those questions coming.

Also across the bottom of your screen, you'll see some other blue buttons that say enlarge slide. I bet you can guess what that one does. Another one that says download slides; again, pretty self explanatory. And a third one that says forward to a friend. Now it doesn't have to be a friend. You could forward the slides to yourself, to a colleague, to someone else who might want an offline copy of the slides for later reference. We encourage you to do that.

And speaking of offline copies, we're on iTunes. You can download this whole presentation audio and all starting about this time tomorrow. We'll have it up on iTunes. Just search for embedded e-cast and you'll find not only this presentation, but all the other ones we've done as well.

So with that, I'm going to turn the presentation over to our first speaker, Toby Foster at Freescale. Take it away, Toby.

Toby Foster

All right. Thanks, Jim. I want to start by describing some of the trends that are driving us at Freescale to develop higher and higher performance device in increasing levels of sophistication.

So much of it is derived from the increase of usage of mobile devices, expected to be 3 mobile devices for every member of the population coming soon. And they're being used more extensively. The traffic rates are increasing every month. So this is driving increased levels of bandwidth all the way back into the core of the network. It's driving more sophisticated applications in terms of quality of service management. There's also increased cyber threat requirements for packet inspection.

So we see from a networking and a telecom point of view, there is an increased requirement for higher levels of performance and higher levels of processing on a per packet basis. So we see those sort of trends within networking and telecommunications on the -- but we also see similar types of trends on the industrial and military side of our customer base, and here we also have higher levels of connectivity: soldiers in the field with multiple data connections, autonomous operation; and also more sophisticated industrial applications between factory control, medical imaging, DSP activities. These are all driving us in the direction of higher performance computing with more sophisticated control of our associates, and that's what Freescale is developing and working in conjunction with Green Hills to enable these devices.

Freescale's highest performance device right now is the QorIQ T4240 communications processor. This device is a 12-core device. Each one of these cores is dual-threaded, so it is a 24-threaded device. Overall, its ethernet capability is -- it's about a 40 gigabit per second class of device. So that's the level of performance it achieves with minimum 64-byte packets with a total I/O Connectivity of about -- of over 50 gigabits per second for larger-sized packets.

This device has an architecture that supports packet handling through what we call the data path acceleration architecture that handles housekeeping-type activities of buffer management and sharing workloads across multiple cores. This allows the cores themselves to focus on value-added tasks. The device also comes equipped with 3 different types of accelerators and has a security algorithm accelerator operating at up to 40 gigabits per second, a data compression engine for application delivery controllers and LAN optimization controllers, operating it up to 20 gigabits per second, as well as the pattern-matching engine for deep packet inspection at up to 10 gigabits per second.

All of this ethernet capability is complemented by a robust set of I/O ports with 4 PCI Express ports operating up to Gen 3 with single route I/O virtualization support as well. Serial RapidIO, commonly used in base stations in military and industrial markets, as well as a set of Interlaken. And then also on the I/O side is our high-speed Aurora debug port. This is something we work with Green Hills closely to enable this high-speed port, which allows real-time tracing to extract -- trace data out of the device as it's generated. This set of ethernet capability and memory map I/O is supported through 3 memory controllers operating at up to 21 33 mega transfers per second, and either DDR3 or DDR3L.

The performance of this device is really derived from its core. This is a Freescale's e6500 Power Architecture core. This is our second generation of 64 bit processor and our first generation of multi-threading. This is a dual-threaded core. And one of the most interesting things about this core and the T4240 is that together they have -- they work together to deliver what is currently the industry's highest CoreMark score for an embedded processor. So you're maybe familiar with EEMBC's, which is a benchmark that largely focuses on the efficiency of the core itself, not the entire SoC, but just the core and the T4240 has posted a score of 180,000 core marks. So that's the highest score for any embedded processor, meaning a device that has integrated memory controllers, ethernet capabilities and SoC.

This is something that we have achieved with using the GCC compiler and that's what the result was. We've published using that compiler, but we've also done this as well with the Green Hills compiler and generally, find the Green Hills compiler to be the best compiler and gives always -- gives us the best results. We currently have results that are 10% higher than this in our back pocket that we have not yet published, but that's what we've achieved with the Green Hills compiler. Across various different benchmarks, we have seen as high as up to 25% improvement using the Green Hills compiler.

So that's the table at the top right of this chart, but there's also at the bottom right is an interesting statement about the performance of this core and the T4240. This is showing what we have measured the same benchmark on an Intel device, and what we have seen in that case is that the performance of the device decreases as the device gets hotter. And that is a characteristic that is not present in the T4 family of devices or in fact, any of Freescale devices.

When Freescale state a performance level or CoreMark performance of 180,000, that's always a level of performance that device delivers regardless of if it's operating at a low temperature or all the way up to its maximum junction temperature. It delivers a constant performance and allows our devices to -- and enables our customers to guarantee the level of performance that is being delivered by the device. That's not something you necessarily see if you are using a device. That's primarily targeted for PCs or servers. So that makes the 180,000 CoreMark score, even more remarkable because it is constant over temperature.

In our next slide -- and I may need Christine to advance it for me. On Slide 6, we have a number of levels of virtualization support added into the T4240, and this exists both at the core level and within the entire SoC itself.

At the core level, we have a hypervisor hardware capabilities built in. So this is a third level of privilege below user mode and supervisor mode, but this will examine requests that operating systems make to have systemwide -- they have systemwide implications such as changing a memory management unit. And the hypervisor will evaluate if that request is allowed or not and either pass it through or block it as it is as the policy is programmed. We support virtual CPUs in this device, the 24 threads allow -- can be isolated from each other and supported by each one having its own virtual memory management unit.

Within the SoC level, there's multiple levels of virtualization as well. We have what I call the Peripheral Access Management Unit, which is an I/O MMU. Its purpose is to evaluate incoming requests from a memory map interface such as the PCI Express port and ensure that certain areas of PCI Express, address space or certain parts, are only allowed into the area of memory that, that particular port is allowed to go into. If there's a programming error and it's trying to access a memory that it does not belong to its partition, that will be blocked by the Peripheral Access Management Unit. And the components of the data path acceleration architecture are virtualized as well, so they can be shared across multiple cores.

These features are complemented by some advanced power management capabilities, and it's certainly a direction that our customers are looking to improve in both, the ability to just consume less power over all, but also the ability to control how much power is being consumed in a programmatic way. So we have levels of power management at all levels within the device itself. At the core level, you can -- there's dynamic clock gating, which means parts of the device that -- of the core that are not being used are not clocked and power is saved kind of under the hood, and the users just benefit from that without seeing any level of performance decrease.

There is also other modes where significant amounts of power can be saved if you're not using features or, in fact, are not using the core at all. Our AltiVec block has the ability to be put into drowsy mode and save power. So drowsy mode is a mode that we've introduced which not only saves the -- not only dates clocks since they use dynamic power, but also saves static power as well. There's various other levels of power savings mode within the core that all have successively longer times to recover from. So the deeper of a sleep you put the core into, the more power is saved.

At the cluster level, which is a group of 4 cores, this can also be -- power can be controlled through changing the frequency of the core -- of the entire cluster, or powering down an entire cluster through putting it in drowsy mode. At the SoC level, there are also capabilities for what we call cascaded power management. So this is a way for the centralized work distributor, which is the queue management unit, to assess the busyness of a core. And if it finds that 4 cores are operating on a workflow but none of them are very busy, it can direct the entire workflow to, for instance, 2 cores and allow the remaining 2 cores to go into drowsy mode for further power savings.

Christine, please advance. This device is equipped with a trust architecture, which means the ability -- it has actually 2 meanings. One of them is protection from theft and the other is assured computing. So protection from theft means the ability for our customer who invest significant resources into an intellectual property into their software to ensure that, that software cannot be reverse engineered and copied and duplicated.

This is implemented through a mechanism of encrypting the boot code, and that is matched against the secret key that is hidden with inside the T4240. So the T4240 will load the boot code and then examine if the key matches and if it does, unencrypts the boot code and execute it. So from that manner, the boot code is hidden. It cannot be de-processed and with that -- because the secret key hidden within the T4 is not known.

The assured computing is even a level of capability beyond that, which ensures that somebody could not go as far as extracting the secret key from inside the T4 through deprocessing. So if you were to shave layers off the T4 to try to find out how those fuses have been blown and what the secret key is, there are mechanisms where that secret key can be zeroed out. This is primarily used in military applications where you are very much concerned about captured equipment not divulging the contents of its software.

Finally, these -- the combination of these 2 features are implemented in a cost-effective manner. This usage of these capabilities means you would not need to use an external trusted platform module. The fact that it's all inside a single SoC means there's fewer buses to probe. Over all, a lower cost solution with higher level of security.

Next slide. Finally, we have the AltiVec technology. This is something that Freescale has had for multiple generations of devices, and we are bringing it back into products that use the e6500 core, such as T4240. AltiVec is a single-instruction, multiple-data block, and everyone on the cores has it. It's -- what it does is it operates on 48 bytes of data at a time and has a 162 different instructions that allow you to combine those in different ways. So it can do additions and permutations of 316 byte vectors all in a single instruction. This is within the -- within the T4 itself, we have 12 of the AltiVec units, and it is one of the ways that we are able to achieve the highest level of performance through our CoreMark score.

Next slide. So I would like to summarize what I have gone through so far. The T4240 is Freescale's highest performance device with 12 cores, 24 threads, capability of 40 gigabits per second or more of ethernet processing capability. We bring the AltiVec technology back into this device, which has been widely used in military and imaging markets, but also has been successfully leveraged in networking applications as well.

AltiVec is one of the reasons that we have been able to achieve the highest CoreMark score of any embedded SoC of 180,000 CoreMark. And we complement this capability with sophisticated power management features to match the power to the processing requirements, as well as virtualization capabilities.

With that, I would like to hand it over to Rob Redfield, who will discuss, from the Green Hills perspective, how Green Hills is enabling these capabilities.

Robert Redfield

Thank you, Toby. Green Hills is really pleased to be Freescale's preferred partner on this impressive, new QorIQ high-performance computing platform. After 32 years of focusing on embedded systems, Green Hills is the largest independent embedded software vendor in the world. And we bring products and expertise that are really strong in embedded optimizations, security and reliability, which are very applicable to this processor family. Green Hills and Freescale have customers who have been and still are successful in deploying thousands of QorIQ-based devices all over the world, such as enterprise routers, industrial automation, aircraft, avionics, intelligent data fusions, simulators, just to name a few.

The Green Hills portfolio for QorIQ is broad and deep. At the top of the screen is our family of -- let's see, are we seeing the -- okay. I'm having a little hiccup on my side here as far as the slides. At the top of the screen is our family of real-time operating systems and hypervisor, INTEGRITY and INTEGRITY Multivisor, there we go. INTEGRITY and INTEGRITY Multivisor at the top of the page, with board support packages, peripheral drivers and middleware, such as our embedded crypto toolkit and networking and routing protocols.

Continuing clockwise, there's the multi-integrated development environment, including the industry renowned Green Hills compilers, which we'll get into in a moment. The Green Hills probe and SuperTrace Probe enable board bringup and high-speed, hardware-assisted debugging and trace debugging, which Toby mentioned, and we're going to get into that as well.

Our 3 global technical centers provide safety and security, design and development in addition to traditional customer support and Quick Start programs. At the 9 o'clock position on the slide is our revolutionary TimeMachine that adds Trace-powered features to the multi-debugger, letting you debug backwards and forwards in the QorIQ program execution. We'll get into that just a moment.

Not shown on the slide is our industry-specific platforms that combined industry certification and technologies for specific focused markets. Examples include the platform for industrial safety, platform for secure networking, platform for wireless devices to name a few.

The INTEGRITY real-time operating system was built from the ground up, with sturdy bones and a modern architecture for you to construct a modular system with a high assurance microkernel foundation. It strongly isolates components with well-defined interfaces between them.

Okay, so what does this mean to you? You can define impenetrable partitions to contain software errors or attacks from spreading to other software components. You can assign resource quotas for individual tasks to guarantee that they will have the percentage of CPU and the memory they need. You can know for certain the worst case interrupt response time.

INTEGRITY was designed for determinism. Other operating systems were designed with old architectures where worst case response time is indeterminable, and their vendors can really only give you average response time. Variances there are often in the milliseconds, which is -- that's hundreds of thousands of QorIQ cycles. With INTEGRITY, you can also control multicore utilization on the T4240 with SMP, AMP, core affinity, mixed modes and other advanced mechanisms. And you can even host multiple guest operating systems, such as Linux, and their applications in secure partitions with our Multivisor secure hypervisor.

Integrity offers a broad and deep support for the QorIQ peripherals and devices, including the networking stacks and security protocols, a whole range of connectivity, file systems, graphics, data transport and much more. Integrity leverages the trust architecture that Toby mentioned earlier for its hardware acceleration units, including the data path acceleration, DPAA, AltiVec, virtualization units and power management.

One special note, INTEGRITY-178B holds the distinction of being the world's only operating system to achieve the pinnacle of software security, that is EAL 6+ Common Criteria for robustness. This hinges on its superior separation kernel. Other INTEGRITY family members are certified for safety or reliability and target different markets like avionics and industrial railway and medical, the markets that Toby was mentioning.

GHNet and GateD networking and routing products are designed for embedded performance and reliability. So for the highest performance, we tap into the QorIQ data path acceleration architecture, DPAA. There's a wide range of protocols including dual-mode security, virtual routing, wireless, just to name a few. And we are, of course, certified IPv6-ready.

The INTEGRITY Cryptographic Toolkit is a complete set of compact crypto algorithms. They can be run as software-only or integrated with QorIQ trust architecture crypto hardware accelerators. To bring you the highest level of assurance, they are validated to FIPS 140-2 Level 1 and are compliant to NSA's Suite B.

To some in embedded, virtualization is relatively new trend, but Green Hills has deployed secured virtualization in embedded systems for 10 years now, and not only does it have a headstart, but it has a unique architecture. Why do I stay that? Because INTEGRITY Multivisor for QorIQ is built on the most secure and reliable separation kernel in the world, INTEGRITY.

So now you can place one or more guest operating systems like Linux in their own secure sandboxes, separated from mission-critical tasks, either on the same core or not. Let me repeat that: INTEGRITY Multivisor does not require the natural boundaries of multicore to securely separate your software components. We can securely separate them even on the same core.

So now your system can combine guest operating systems with their popular stacks and environments with mission-critical tasks, and your system inherits INTEGRITY's architectural advantages like secure separation for robustness, guaranteed allocation of CPU and memory, highest performance in determinism, fast boot and instant-on features, trusted communication channels between partitions and so on. In addition, we're seeing our networking customers today using Multivisor to enable security-certifiable data and network services, and always-on agents for health monitoring and remote servicing.

Multivisor has a proven history of leveraging QorIQ trust architecture virtualization features, such as PAMU and virtual CPU MMU, features that Toby was mentioning earlier.

So let's move to the kinds of tools you can use to build high-performance systems on QorIQ. The multi integrated development environment is all about saving time you, about leveraging hardware accelerators and producing the high-quality code. MULTI gives you deep visibility into your software on in the e6500 cores and threads. You can debug forward and backwards in program execution with TimeMachine using 0 overhead trace data. You can use the same debugger to see running tasks or you can stop the entire processor and step -- lockstep through execution. And because MULTI uses OS-neutral debug servers, you can debug applications on INTEGRITY,Linux, VxWorks, Enea OSE, homegrown OSS and bare board with no OS now, high-performance computing naturally requires an optimized tool set, and cogeneration. Green Hills compilers continually set an embassy of performance records, including the T4240 core mark scores that Toby mentioned earlier. We have 32 years experience in writing, optimizing compilers for C/C++, Ada, and for some of you, Fortrend, even. And we'll talk about our AltiVec support a little bit later.

MULTI contains components that we've created and perfected over the years. Easy to use, powerful. So find bottlenecks with the Profiler. Be alerted to memory leaks. See highlighted dubious code that may compile, but it will bite you later. See your threads or ports and tasks on a timeline. They are all integrated together, and with a click, you get to the source code that's under the question. Our instructions have simulators chips with MULTI, so that you can build and debug and run on the core when the QorIQ board is unavailable. Many features like Flash programming and hooks to your favorite editors or source code management systems. You can run like Simulink models through the MULTI debugger. You can use Python scripting to externally control MULTI. And then last, but certainly not least, MULTI was recently the first to achieve precertification as a qualified tool for the highest level functional safety on several standards such as industrial IEC 61508.

When it comes to speed divisibility, into your software, TimeMachine is simply unmatched. In fact, QorIQ is unmatched because no other processor in its class supports TimeMachine. So Toby mentioned the trace fabric and we take full advantage of that. So what does this mean to you, the developers? Through the high-speed trace interface found on the T4240 you have unprecedented visibility into software running on the core and that visibility comes at no cost, that is it's non intrusive to the processor and requires no recompilation. In the same familiar debugger, TimeMachine adds blue arrows for stepping and running backwards. You can set break points and run backwards, it's amazing. You can't TiVo backwards and forwards in the execution until you find the problem. Plus our other tools, such as a Profiler are now -- they're powered with the same trace data and show actual data with 0 processor overhead.

So in lieu of a demo here, in front of you all, check this out. So in traditional debugging, when software acts unexpectedly, on T4240, what do you do? As a debugger, you probably insert printf’s or you add some test scaffolding code and you rerun. Well, you probably will get a different result or if you're lucky, you might get the same result, but then you need to sprinkle in some more test code to figure out what's going on and zero in on the problem and you'll rerun again. Hopefully, you are able to rerun and get the same results.

TimeMachine is a different model. It's a different workflow. With it, you don't need to add test code. Instead, an exact data record of every CPU instruction is saved in a trace lock. Now all you have to do is you click in there and you get the debugger with the source code at that moment in the execution. And as mentioned earlier, now you can step and run backwards and forwards in execution, test hypothesis and this is all on the actual code that ran on the processor. So from here and from the source code, you can click to see or toss system events along the timeline or function flow along the timeline. You can use profiling and other tools again, with 0 overhead. And because trace data is saved into the log file, you can give that to other team members, either on the same room or another part of the world. And with TimeMachine, they can run that. They don't need to have the hardware or the whole test scaffolding to reproduce exactly what you see and what you're working on.

As I mentioned Freescale designers in their wisdom, they designed in the industry-standard trace fabric to enable probes to gather trace at high speeds. The Green Hills super trace probe, it doesn't even break a sweat sucking in -- it's an amazing 1 -- 1.25 gigabytes of trace data per second. And it's able to capture 12 seconds of T42 execution, which is about 40 billion instructions. TimeMachine and SuperTrace Probe also give you the capability for multicore and multithreaded visibility using the tools that I just showed you. And you have the option of running them synchronously or asynchronously across cores and threads. So this is deep visibility into your software.

The Green Hills probe does not use trace data. It's all about deep visibility into J-Tag debugging and run control connected to MULTI. It's especially useful for board bring up, debugging and device driver work. It's multiuser, multicore and downloads your program at a really high speed of 10 megabytes per second. So you don't have to wait around and grab a coffee every time you want to do another run. It too leverages T4240 trust architecture that Toby mentioned, in this case, the secured debug controller.

So we're really pleased of Freescale brought back AltiVec on this processor. Many of our customers in different industries have enjoyed its DSP-like performance. We support AltiVecin 3 ways: optimizing C and C++ compilers assembler, intrinsics, simulator, coupled with the MULTI debugger data and memory viewers. The second way is through the Green Hills compiler vectorization. And then there's INTEGRITY, which among other things, takes care of AltiVec register housekeeping, so that you don't have to.

So let's just take a quick look at the compiler vectorization. So the Green Hills compiler vectorization, when it's guided with pragmas that you insert into the code, it converts certain loops into optimized AltiVec instructions, yielding up to 4x increased performance. So let's look at the simple dot product example. On the left, ordinary C code generates this assembly and runs in 21 cycles. On the right, with the pragmas noted in the green font there, so just 3 of them, and with the vectorization flag turned on, the compiler generates this assembly code, which you'll see is dense in AltiVec instructions, running at only 5 cycles..

So creating quality, embedded software on the T4240 within schedule and budget, with all these cores and accelerators, it's not easy. Our 3 global technical centers offer trusted visor support models, including 10-year customer branch support to you, quick-start programs, BSP development, optimization consulting. And we can help you with deep consulting through any of the industry safety and security certifications that you might have to go through.

So let's summarize the takeaways here in neon lights. Highest possible performance. This is through software tools, middleware and our RTOSs that leverage the T4240's acceleration engines. Unprecedented visibility to find and fix bugs very quickly on a 24-core system with a beautiful trace fabric that enables deep visibility. And whether your system requires high reliability or certified safety and security, it's all got to start at the lowest level software foundation and that's the high assurance microkernel working in harmony with Freescale's trusted architecture. Our trusted advisors can help you get the most from the T4240, whether its performance or safety or security, and we've actually thrived on this leading edge of embedded processor technology for 32 years. And we look forward to working with you on your project. Thank you. Jim, I'm handing it back to you.

Jim Turley

All righty. Well, thank you, Robert, and also to Toby, our Freescale representative. Man, that's a lot of stuff there. It makes me wish I had a real job again, start doing some engineering. And to our audience members, we've got a couple dozen good questions. I'm going to start to plow through those. But don't let that discourage you. If you've got more questions for our speakers, go ahead and type them in there and we'll get to as many as we can.

Question-and-Answer Session

Jim Turley

Toby, I'm going to start off with one for you. It's kind of a silicon-related question. So this seems like it's appropriate for the Freescale guy. Let's say I'm excited about the T4240, I'm excited about INTEGRITY, I want to get started, I want to start developing. It seems like the first step would be some sort of evaluation platform. What's available along those lines?

Toby Foster

Yes, Freescale has one evaluation platform for the T4240 and 2 others that are in process right now. Our existing evaluation platform is a ATX form factors, the size of a desktop, PC-type of thing with a high level of flexibility for different [indiscernible] configurations. So that's available now. We've had that out for a few months and we're selling that for $4,000. And then we have 2 other cards that are coming, that are significantly less expensive, one we call our reference design board, which is a one you form factor with less flexibility, but quite a bit less cost as well. And we are also in development of a PCI express card.

Jim Turley

Okay. So one board available now and different versions to come.

Toby Foster


Jim Turley

Good, good. Robert, I'm going to bounce over to you quickly here. We talked a lot about debugging features that the Green Hills software provides. The Freescale chips in general from the QorIQ family all the way back to the PowerQUICC family, they've always had the pretty good on-chip debugging features built into the silicon. Were those useful when you're creating TimeMachine for this new QorIQ?

Robert Redfield

Oh, yes, absolutely. In fact, they are essential. And as we pointed out, the QorIQ family and it continues with the T family, is unique in their class, with this sort of standard, trace interface that, with the right kind of software, you can do some really amazing things.

Jim Turley

Yes, it does sound pretty impressive. A hardware question for you, Toby. We talked a little bit about the variable power consumption of the chip. I've actually got some questions of my own about that. But one of our audience members asks, what's the lowest possible power consumption on the T4240 , what can I get it down to?

Toby Foster

Yes, you can have quite a few knobs to control power if -- the lowest power consumptions are achieved -- can be achieved in around 21 watt range. And so that's using the entire chip. So with the 12 core version of it, the T4240 and the -- it also comes in a 8-core version with 16 threads, it's called the T4160, and that one can be, as low as about 16 watts.

Jim Turley

Well, that's a pretty reasonable for 12-core, 24-thread device. Robert, another software question for you, before I just asked you about the debug features AltiVec. Though it's another one of those things that has been on a lot of power architecture devices in the past, but I don't think we've seen it on communications devices for a while. Clearly, you supported here that Green Hills with previous experience with AltiVec that you could reuse or was -- does this mean new development for your group?

Robert Redfield

It was both, but yes, we definitely reused it. In fact, we were an early supporter with AltiVec inception back in the late '90s. And so, we've actually supported it continuously up into the T4240, where some new capabilities were added in the AltiVec instructions which, of course, we jumped all over and are taking advantage of.

Jim Turley

Okay, cool. Understanding the T4240 as a brand new device, Toby, how long do you expect it to be in production? Is this the kind of thing where there's a 2-year guarantee or 5-year guaranteed lifespan for it?

Toby Foster

Yes, this is an area that Freescale, sometime ago, couples of years ago, recognized there were some significant advantages in the way that we ran our business model. So we guarantee our networking devices will be available for a 10-year period of time. Specifically, the T4240 will be available in, at least, as long into 2022. It's hard to even say that year so far into the future. But our experience is that our customer base wants to continue to buy the exact identical version of the device with no changes to it for decades. And that's an easy thing for Freescale to support because our business is really built on all the customers wanting to do that. They're all in sync with each other. If you're in the business of PCs, that is quite a bit harder to do because the business model requests that you improve the processor, at least once every Christmas season. And Freescale's business model is maintained a version of this -- maintain the identical version of it, shipping for 10 years, so 2022 for the T4.

Jim Turley

Man, 10-year life span. Yes, as you say, you're not tied to the fashion cycles of PCs or smartphones or anything else. This is heavy industrials or rather embedded stuff. And you're right, your customers are expecting these chips to be around for quite a while. Robert, I've got another trace question for you. Do you require the SuperTrace Probe to be able to use TimeMachine? Do I need that?

Robert Redfield

No, you don't. You can actually, as I mentioned, we ship an instruction set simulator with MULTI. And so you can drive TimeMachine with that data. Now, obviously, that's not going to be nonintrusive as it is when you use the SuperTrace Probe coming off the high-speed Aurora port on the board. But functionally, it's still amazing, and it gives you really deep visibility.

Jim Turley

Okay, and kind of a similar question. The Green Hills Probe V3, do we have new firmware that supports the T4240 QDF.

Robert Redfield

Is that question the SuperTrace Probe or the Green Hills Probe? Well, let me just -- I can just summarize. For the Green Hills Probe, yes, it does support the evaluation board that Toby mentioned and it's available in our latest firmware release.

Jim Turley

Yes, you guessed right, that was indeed the question. Yes, Toby, I had threatened 1 minute ago in asking you little bit more about the software configurable power consumption of the device. As a programmer, that strikes me as a really interesting feature that I could somehow dial in the power consumption of my device, without spending another hour describing it. Give me an idea of what sort of knobs and dials I got at my disposal to do that?

Toby Foster

Yes, the most powerful capability that we've added into the T4240 and its derivative device is a mode that we call drowsy mode. And so what this does is this affects the ability to -- this reduces static power. And typically, for a device in this process node, you would have the power consumption kind of equally split between dynamic power, which is related to clocking, and static power, which is just there as long as power is provided. So you're not typically able to control the static power component. If it's powered on, you are consuming static power. So that's what the drowsy mode is addressing. This is a mechanism where we allow the ground plane as part of the device to float and it approaches the VDD power level, and ends up minimizing -- almost entirely reducing the static power consumption. So we can do that at the turn off parts of the device. Particularly the AltiVec unit, we can do it at the core level, and we can turn off an entire cluster or a group of 4 cores, so we can implement smaller versions of the device. Our customers can disable these things as they need. So this is useful and we see a several different usage models for it. So one of them being -- there's not much network activity in the middle of the night, 1 a.m. to 5 a.m. or something like that. So from the total cost of ownership point of view, you can reduce your electrical consumption by disabling parts of the device that you don't need. That's one of the uses for it. Probably, the more important use for it is trying to respond to environmental problems in the cabinet or central office data center, et cetera. So you may have a case where the air conditioning fails and the ambient temperature is increasing and you need to maintain that the device stays within its junction temperature, and one of the ways you can do that is by disabling a cluster for instance, to reduce its power consumption and minimize the amount of consumption rate and keep it's junction temperature. So it's both electrical cost reduction capability, as well as a responding to environmental problem capability.

Jim Turley

All righty. And following up that complicated question with a simple one, you mentioned the current device has 12 power processor cores in it, are there going to be future spin offs that have fewer cores?

Toby Foster

Yes, we've typically implemented our product family in that manner and we do the most complicated flagship product and then have several derivatives from it. So the T4240 is a 24-threaded. It also drives a 16-threaded version of the device. And then we also have an 8-threaded version of the device, called the T2080, which follows this one by 6 month or so. And then there will be the -- our lowest member of the family comes and it's this T1 series of the devices that come as dual and quad cores.

Jim Turley

Okay, got it. Our next audience question is probably aimed at Robert. So we'll let you handle this one. It has to do with trace tools. We have an audience member asking about Nexus Aurora-based trace tools. How high is the core or system intrusiveness if I'm using Nexus Aurora-based trace tools?

Robert Redfield

Well, and it's zero intrusiveness. So the Aurora high-speed trace interface operates independently and is nonintrusive to the core. So that's -- it's a beautiful feature of visibility. Because in past, if you look at software and hardware systems, since day 1, there was always the side affect of looking at what's going on. The deeper you look, the more intrusive it became often. And so that's what's beautiful about the Nexus Aurora interface.

Jim Turley

All right. And as long as we're on the subject of software and acronyms, do you have support for Mcape?

Robert Redfield

That one, I'd have to take back and follow up with an answer. I'm not familiar with that.

Jim Turley

No problem, got you on that one. Okay, gentlemen. Last call to our audience members. We've got a couple of minutes here to squeeze in the last few questions before we have to let our speakers go. Also, I'll remind the audience questions with short attention spans -- audience members with short attention span, we've got a survey coming up. The last slide we're going to show is the link to our survey. We invite you to click on that, make sure you tell us how you liked it. What's going well, what's not, so forth, that kind of thing. Back to our audience Q&A, to use the real-time debugger via the Aurora port, does a design have to sacrifice [indiscernible] channel. Do I have to give up [indiscernible] channel to use that?

Robert Redfield

That's a good question. I've heard those -- that kind of discussions and I don't know the answer. But if that person can contact me one way or the other, we'll definitely get an answer.

Jim Turley

No problem at all. And Toby, you may have answered this one for me, but I didn't write it down. We talked about low power consumption, variable power consumption and so forth, can you give me a typical number for the T4240, is that something you could ballpark?

Toby Foster

Yes, that is a number that I was previously stating, which is around 20 watts. And so typical is what we expect to see the device doing when it's in the lab and in a air-conditioned room. So that's -- and that's -- that particular power estimate is associated with it's -- there's a 1.5 gigahertz speed bin. That's about 5 watts higher at its 1.8 gigahertz speed bin. So that's a -- and then the power can be quite a bit higher as the junction temperature increases. There's a pretty strong relationship between, specifically, the static power component with increased junction temperatures. So at the typical level, that's where we see the lowest power numbers at lower junction temperature.

Unknown Analyst

Okay, terrific. Robert, I think, I can squeeze in one last question before we have to wrap this up. Toby, mentioned the evaluation board for the T4240 does Green Hills have an INTEGRITY BSP for that eval board?

Robert Redfield

We don't have it available in the general availability right now. However, what we are doing with our early customers is they're using the rest of our portfolio to get started. So our software development tools, MULTI and TimeMachine and our Probes and all the other multi-IDE components are available now. And for our early customers, that's a good point or good phase to be using them as the BSPs rollout.

Jim Turley

Alright, terrific stuff. And good staff all the way around. We had even more audience questions that we couldn't get to, but some of our speakers may be able to answer those offline. So fear not, if we didn't get to your question today. And again, we'd like all of our audience members to fill out a little survey for us. You can also contact us, at the And as we said at the top of the show, this entire e-cast, just like all the ones we do, is available on iTunes. Just go to iTunes and search for embedded e-cast and you'll find us there. So to wrap-up, I'd like to thank our 2 speakers, Toby Foster from Freescale Semiconductor and Robert Redfield from Green Hills Software for spending their time and enlightening us on these devices. For all of us here at OpenSystems Media, I'm Jim Turly. Thanks, everybody, for attending.

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