Intel Soon To Drop Weapon Of Mass DRAM Destruction

| About: Intel Corporation (INTC)
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Some of Intel's upcoming 3D XPoint product specifications have leaked.

Nearly the entire world is disappointed because they are reading them incorrectly.

This represents a potential investment opportunity.

Specifications on Intel's (NASDAQ:INTC) first 3D XPoint product - the Optane 8000p - recently leaked to the public. Judging by an Intel road map leaked months prior, this appears to be the low-end "Stony Beach" product with just two lanes of PCIe connectivity:

Once again, the average Joes proved that they have no idea what is about to happen even though Intel and Micron (NASDAQ:MU) have spelled it out for us - quite literally. This lack of understanding is illustrated by some choice quotes from the subsequent discussion:

I thought this was going to blow away the Samsung (OTC:SSNLF) 950 pro. Instead, the numbers are actually pretty similar. -Sam

Even compared to midrange (Samsung) 850 Evo, it is just laughable, really Intel you are that pathetic? -Pitcairn The Immortal

Those numbers are pretty pathetic (to be honest). I was hoping for 2500+ -Antonio Montana

The issue here is that these people are comparing the Optane product to existing flash drives ("SSD") that are used for file storage. And I can't blame them as the conclusion in the article actually guides their train of thought by including such a comparison. However, in the periphery of this leak is something that nobody else noticed - the branding.

This is Optane Memory and not Optane Storage. That is, they're using it in lieu of DRAM - not SSD. For those of you who are new to many years of my tinfoil hat musings on the matter, allow me to recap: Intel and Micron have filed a bunch of patents for a two-level memory ("2LM") system that, in addition to a whole suite of other benefits, mitigates the need for most standalone DRAM. They even demonstrated the technology earlier this year. But it is best summarized in one of the many patents:

The focus of this approach is on providing performance with a relatively small amount of a relatively higher-speed memory such as DRAM while implementing the bulk of the system memory using significantly cheaper and denser non-volatile random access memory (NVRAM).

Intel's own Rick Coulson characterized this opportunity in a talk at Stanford:

We did a little demo a while back where we took a PC and restricted it to 256 megabytes of memory. And we ran a side-by-side demo with an 8 gig(abytes of memory) system. You couldn't tell the difference. And the little meter on the paging - 200,000 pages a second - page misses a second. And that was okay if you're fast enough.

I've highlighted that "200,000 pages a second" specification above because the leaked Optane 8000p numbers handily exceed this requirement. For applications that require more I/O, the "Mansion Beach" four-lane version is coming by year's end. I would also expect to be able to multiply performance by installing multiple modules.

It is important to note that Intel is mostly focused on write speeds because the patents outline the need to use an eDRAM "memory side cache" that, in addition to increasing performance, helps to coalesce writes in order to prevent the 3D XPoint from wearing out and using too much energy. This memory side cache was recently implemented in Skylake, albeit without explanation.

Instead of being a level 4 cache, the eDRAM is now what Intel calls a memory side cache. In Broadwell, the eDRAM was notionally connected to level 3, to store data that the level 3 cache no longer had room for. In Skylake, the eDRAM is now connected between the integrated memory controller and the "system agent;" the portion of the processor that handles, among other things, cache coherence (ensuring that different cores see a consistent view of shared data).

With this new design, the eDRAM is always coherent, since it is privy to all writes made to main memory, regardless of which core makes them. This also means that it can cache any data, even if it's stored in memory that is marked as "uncacheable" by the operating system. The design also enables both PCIe devices and the display engine to read to and write from the cache.

Intel's representatives were strangely reluctant to describe what all these changes meant in real terms.

-Peter Bright,

But we know what they did last summer from Intel's US Patent 8,830,716:

Because people won't be able to discern the difference, Intel is now free to drop the big and expensive external DRAM bus from systems where Optane meets capacity and durability requirements. Let that sink in for a moment. Pictured below is the underside of an Intel Kaby Lake CPU package. While there are more than a thousand connections, more than half of them won't be required if the external DRAM bus is eliminated. This will result in considerable cost savings, not to mention how much less space that will be consumed.

Unfortunately, it might not be all puppy dogs and ice cream as there is a recent development on the durability front. A recently published Micron patent application reveals likely 3D XPoint durability specs. Unfortunately, it does look like they have some unanticipated problems with the technology:

Some embodiments include architectures in which two or more memory array decks are vertically stacked. One or more of the stacked decks is configured to have different operational characteristics relative to others of the stacked decks. For instance, one or more of the decks may be configured to have rapid access times suitable for utilization in XIP (execute in place) applications and/or dynamic random access memory (DRAM) emulation applications, and one or more others of the decks may be configured to have stabile, possibly slower access, storage suitable for utilization in long-term storage applications. Further, one or more of the decks may be configured to have more endurance than others of the decks. For instance, one or more of the decks may be suitable for a lifetime of approximately 100,000 cycles, whereas one or more others of the decks may be suitable for about 1,000,000 cycles (in other words, at least one of the decks may have a durability of at least about 10-fold more cycling times than another of the decks). The difference between the endurance of the decks may result from structural differences between the decks. For instance, a deck with higher endurance may have reduced thermal disturb and/or other memory-loss mechanisms as compared to a deck with less endurance. However, the deck with less endurance may have other advantages (for instance, faster access times, etc.) as compared to the deck with higher endurance. Accordingly, each memory array deck may be tailored for applicability relative to specific memory functions.

For reference, flash memory durability typically runs in the single thousands to tens of thousands of write cycles depending on cell size and type. This is not even close to the specification that is required to function as system memory - even with an eDRAM cache.

If the numbers from this Micron patent application are realistic, then I expect this to impact the bottom line for 3D XPoint products since this essentially restricts the "DRAM replacement" qualities to half of the chip (the lower deck). So a 16GB Optane memory product could require two 16GB XPoint chips.

In this case, I would expect to see a hybrid product - 3D XPoint and 3D NAND - in order to leverage the lower-durability deck of the XPoint as high-speed cache for the flash storage (as 100,000 cycles is still much better than 3D NAND). Alternatively, they could use the low-durability deck for read-only portions of the operating system. It certainly won't go to waste but this is definitely a blemish for the technology.

It is important to note that, even though this was just recently published, this application was filed in March of 2015. So there is a possibility that this issue was solved between then and now. It is also possible that the provided numbers are intentionally misleading (i.e - the "10-fold" factor seems to be more of the point). Previous phase change memory patent applications from Intel and Micron pegged durability in the range of 100 million cycles, for example. We simply don't know what the number will be but I wanted to bring it up for the sake of full disclosure.

Potential disappointment aside, this still blows the traditional DRAM out of the water from a cost and space perspective. If people truly can't discern the performance difference, then it certainly makes sense for Intel to sell the product that is cheaper to manufacture. Putting the bulk of system memory on the PCIe bus (or some other serial bus) just makes more sense from every angle when there exists a solution to maintain performance.

I expect that there will be less impact to system architecture in the high-performance computing space where 3D XPoint is more likely to augment existing designs with new capabilities instead of redesigning for better cost and size. On the other hand, in the mobile space - smartphones, tablets and laptops - will see dramatic cost and space savings through adoption of 3D XPoint. This is described by Intel in one of their patent applications:

DRAM packages such as dual in-line memory modules (DIMMs) are limited in terms of their memory density, and are also typically expensive with respect to nonvolatile memory storage. Currently, to increase the size of system main memory requires multiple DIMMs, which increases the cost and volume of the system. Increasing the volume of a system adversely affects the form factor of the system (e.g., large DIMM memory ranks are not ideal in the mobile client space).

Side bar: the rest of this patent application is worth a read as it foreshadows much of the other things that Intel has in store for us, including asymmetrical big-little core CPUs as well as memory compression and de-duplication.


The Optane Memory specifications shouldn't be compared with storage products of any sort. While the performance numbers appear meager, realize that there will be a large memory side cache sitting in front of it. Current SSDs already have the luxury of this sort of performance enhancement in their numbers - this Optane device does not.

Also realize that the Optane 8000p is an entry-level "two-lane" device that will replace DRAM in low and mid range devices. Current devices in this range typically come equipped with 2 to 8GB of DRAM. Intel is moving this bar up to 16 to 32GB. More importantly, they're also adding non-volatility, so you'll never need to wait for an app to load again - they'll always be loaded in memory and ready-to-go with a delay that is imperceptible from instantaneous.

Intel has its ducks in a row for some looming disruption that will likely do very bad things for DRAM makers, depending on how the final 3D XPoint specifications play out. I suspect that Micron's recent poison pill was engineered in anticipation of this event. Someone might try to scoop them up after the bomb drops - or perhaps before, depending on how much they want this.

To sell or not to sell - just realize that Micron has the upper-hand in this ordeal because they have the only call option on IMFT.

Disclosure: I am/we are long INTC, MU.

I wrote this article myself, and it expresses my own opinions. I am not receiving compensation for it (other than from Seeking Alpha). I have no business relationship with any company whose stock is mentioned in this article.