I discussed in a May 8, 2017, Seeking Alpha article entitled "Rudolph Technologies Will Emerge As Leading Micro-Cap Semiconductor Packaging Equipment Supplier" the importance of advanced semiconductor packaging. One example is Wafer Level Packaging (WLP). According to our report entitled "Flip Chip/WLP Manufacturing and Market Analysis," 20 billion ICs were manufactured and incorporated into these packages in 2014, which should more than double to 47 billion in 2020.
By way of illustration, the number of WLP in iPhones has increased over 20 times in the last decade. The original iPhone in 2007 incorporated two WLPs, while the iPhone 7 in 2016 incorporated 44 WLPs, as shown in the graphic below.
Another advanced packaging technology is 2.5D and 3D packages, which stack different chips in a vertical manner (as opposed to WLP where they are packaged side-by-side), as shown in the graphic below.
Because of the complexity of converting process technology from a planar directly to a 3D package, companies initially moved to an intermediate package, appropriately termed 2.5D IC. Xilinx (NASDAQ:XLNX) released the first commercially available 28nm, 2.5D Stacked Silicon Interconnect (NYSE:SSI) device in 2011.
Although 2.5D technology was originally implemented as a bridge technology between 2D and 3D ICs, they have evolved as a package solution that co-exists alongside 3D ICs.
A 2.5D package uses a silicon interposer, which is placed between the substrate and the dice, where this silicon interposer has Through-Silicon Vias (TSVs) connecting the metallization layers on its upper and lower surfaces. A TSV provides a vertical electrical interconnection passing through a silicon wafer or die. These TSVs are manufactured in wafer form and filled with Cu.
With a 3D-ICs, the ICs need TSVs to connect active die with package substrates. With a 2.5D package, only the interposer needs TSVs, enabling the use of existing die designs.
According to our report High-Density Packaging (MCM, MCP, SIP, WLP, 3D-TSV): Market Analysis and Technology Trends, more than 500 million 2.5D packages were shipped in 2016 but only 50 million 3D packages.
I'm not speaking of the use of 3D technology for Micron Technology's (NASDAQ:MU) Hybrid Memory Cube (NYSE:HMC), in which GlobalFoundries (NYSE:GF) handles the TSV formation process and other steps for Micron's HMC. I'm speaking of an integration of logic and memory chips stacked vertically in the same package.
It is important to notice according to the graphic illustration above that with 2D, individual discreet Memory and Logic packages are mounted on a substrate. With 3D, they are mounted vertically, and with 2.5D they can still be mounted side-by-side but integrated on the interposer and interconnected.
Traditional packaging houses offer IC packaging services on the open market. These are OSATs, or Outsourced Assembly and Test. In 2016, they accounted for more than 50% of all IC package assemblies. Leading OSAT companies include Amkor Technology (NASDAQ:AMKR), ASE (NYSE:ASX), SPIL (NASDAQ:SPIL), and STATS ChipPAC
Several years ago, TSMC (NYSE:TSM) entered the advanced packaging market followed by other foundry vendor Intel (NASDAQ:INTC) and now Samsung Electronics (OTC:SSNLF). All three companies provide turnkey service for its 2.5D packages, offering customers a total package solution.
How the memory landscape will change
Currently packaging houses get the completed wafers from an IC manufacturer and ultimately cut it into individual chips to be placed in the package. Because the price of logic chips is significantly higher than a memory chip, it is the logic suppliers that contract with the OSAT, purchase memory wafers directly from manufactures, then send their own completed wafers containing logic chips to the packaging house for insertion on an interposer (2.5D) or substrate (3D) package.
Logic chips include CPUs and GPUs from companies such as Intel, AMD (NASDAQ:AMD), Nvidia (NASDAQ:NVDA), or Qualcomm (NASDAQ:QCOM). The logic company now controls the sale of the package, which is then inserted into servers, PCs, or smartphones, and then sold to end users.
So, instead of memory manufacturers selling directly to server, PC, or smartphone customers, they sell to logic chip companies that sell to these end products. Memory companies may lose a portion of their supply chain flexibility, particularly pricing.
The graphic below illustrates the changing memory landscape.
Winners of this new shift in the packaging landscape are the logic IC suppliers. If they are using an OSAT packaging house, they gain because they dictate pricing from memory suppliers, purchasing from them completed wafers that don't have to be diced and individually packaged, which is added value to the memory suppliers.
If TSMC or Intel foundries are used, these companies change the landscape further because these companies also make logic chips. Here, benefits to these companies are even greater. An added advantage for these companies is reduced costs because they would have a better sense of design for manufacturing all the way from the IC chip design to the foundry process and to packaging. Individual P&L would be integrated.
The biggest beneficiary is Samsung Electronics because the company makes both logic and memory chips. The vertical structure of the company, which has its own end applications (smartphones), would further reduce costs and improve margins.
The losers would be Micron Technology and SK Hynix.
2.5D and 3D packaging is a reality and growing strongly. We project demand for 2.5D will exhibit a compound annual growth of more than 50% between 2013 and 2020. Shipments will increase 300% between 2016 and 2020. For 3D packages, shipments are projected to increase more than 700%.
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I wrote this article myself, and it expresses my own opinions. I am not receiving compensation for it (other than from Seeking Alpha). I have no business relationship with any company whose stock is mentioned in this article.
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