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Critical EUV Milestone: Implications For Semiconductors

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  • ASML successfully demonstrated a 250-watt EUV source recently.
  • The company is claiming affordable use relative to conventional technologies.
  • Industry observes are divided on EUV's realizable cost benefits.
  • EUV,if cost effective, will change the dynamics of semicondutor supply line.

ASML Holding (NASDAQ:ASML) recently achieved a key milestone by demonstrating a 250-watt extreme ultraviolet lithography, or EUV, source at Semicon West Trade show. It’s quite a big deal as hitting the 250-watt mark was the key barrier in driving a material throughput using EUV process. However, it should be noted that productivity of EUV system also depends on “availability” that relates to debris management.

Picture Credit: eetimes

Michael Lercel, director of strategic marketing at ASML, said the company has demonstrated 250 watts "rather consistently by really understanding the conversion efficiency in the source and putting the right controls in place." The source is not being shipped as of now.

EUV has been in the spotlight for years as the technology can eliminate the need for multi-patterning in semiconductor manufacturing that can result in lower manufacturing costs.

Note that shrinking the node has been putting quite a pressure on semiconductor manufacturer’s spending budget in recent times. The cost to design a 7nm chip is nine times higher than designing a 28nm chip; multi-patterning is the key contributor for such cost disparity.

Although EUV tools are expensive – around $100 million each – a 250-watt source will turn the cost benefit in EUV’s favor compared to multi-patterning using immersion lithography tools. With a 250W source, an EUV stepper can be able to process ~100 wafer-per-hour, which should allow for affordable use when matched with other lithography technologies.

“If you look at the cost of doing multiple immersion lithography steps, coupled with the process steps—the cleaning, the metrology—we believe that EUV is less costly per layer versus triple patterning immersion, and certainly quadruple patterning and beyond,” noted Lercel.

Too good to be true?

Yes, there’s a catch. At 5nm, cost benefits may not be realized as double pattering might be required at 5nm. Higher

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