Critical EUV Milestone: Implications For Semiconductors

| About: ASML Holding (ASML)


ASML successfully demonstrated a 250-watt EUV source recently.

The company is claiming affordable use relative to conventional technologies.

Industry observes are divided on EUV's realizable cost benefits.

EUV,if cost effective, will change the dynamics of semicondutor supply line.

ASML Holding (ASML) recently achieved a key milestone by demonstrating a 250-watt extreme ultraviolet lithography, or EUV, source at Semicon West Trade show. It’s quite a big deal as hitting the 250-watt mark was the key barrier in driving a material throughput using EUV process. However, it should be noted that productivity of EUV system also depends on “availability” that relates to debris management.

Picture Credit: eetimes

Michael Lercel, director of strategic marketing at ASML, said the company has demonstrated 250 watts "rather consistently by really understanding the conversion efficiency in the source and putting the right controls in place." The source is not being shipped as of now.

EUV has been in the spotlight for years as the technology can eliminate the need for multi-patterning in semiconductor manufacturing that can result in lower manufacturing costs.

Note that shrinking the node has been putting quite a pressure on semiconductor manufacturer’s spending budget in recent times. The cost to design a 7nm chip is nine times higher than designing a 28nm chip; multi-patterning is the key contributor for such cost disparity.

Although EUV tools are expensive – around $100 million each – a 250-watt source will turn the cost benefit in EUV’s favor compared to multi-patterning using immersion lithography tools. With a 250W source, an EUV stepper can be able to process ~100 wafer-per-hour, which should allow for affordable use when matched with other lithography technologies.

“If you look at the cost of doing multiple immersion lithography steps, coupled with the process steps—the cleaning, the metrology—we believe that EUV is less costly per layer versus triple patterning immersion, and certainly quadruple patterning and beyond,” noted Lercel.

Too good to be true?

Yes, there’s a catch. At 5nm, cost benefits may not be realized as double pattering might be required at 5nm. Higher EUV equipment costs along with patterning costs can make EUV expensive, or at par with conventional patterning techniques. However, this opinion comes from an author working for Mentor Graphics (OTCQB:MNTR), and understandably, it isn’t the most objective opinion as EDA companies can take a hit in case EUV is adopted.

But, the argument is also backed by Stephen Renwick, director of Imaging Physics at Nikon Research Corporation of America. He points out that multi-patterning might be needed at 7nm and will certainly be needed at 5nm. See the graph below for cost comparison of EUV and conventional techniques.

Source: Canon

It can be seen that EUV results in much lowers cost per wafer. However, the cost per wafer is higher compared to conventional techniques when double patterning is added to the equation. However, it should be noted that the test features 15nm half-pitch lines. Multi-patterning costs will be much higher for 7nm and 5nm. Therefore, it is not possible to draw clear conclusion about the economics of using EUV.

Nonetheless, EUV will be at clear advantage if foundries manage a way to avoid double patterning at 7nm.

What does it mean for semiconductor companies?

Many companies across the industry will be affected by this development. ASML will directly benefit if industry adopts EUV, and it turns out to be a cost effective approach.

Semiconductor equipment manufactures

Dynamics of semiconductor manufacturing companies will also change as EUV reduces the need for complicated manufacturing machinery. Deposition and Etch machinery is required in case of masking and multi-patterning. In case of adoption of EUV, the demand for the deposition and Etch machinery of Applied Material (AMAT) and Lam Research (LRCX) can go down.

However, note that as EUV might require patterning at 5nm, the effect on semiconductor equipment manufacturers will be a trough rather than a secular decline. Another point to note is that both these companies are exposed heavily to DRAM and NAND markets. The effect of EUV adoption might not be severe as memory companies are still around 16nm. And Micron notes that,

nothing on their current road maps requires EUV, so at this point it is just a potential for cheaper or more efficient manufacturing, not a looming roadblock.”

All in all, the adoption of EUV isn’t expected to hurt semiconductor equipment manufacturers materially as they are exposed to NAND and DRAM, which are on a lagging node.

What about EDA companies?

Electronic design automation, or EDA, companies can also take a hit. Multi patterning has some inherent blurring limitations that are corrected using EDA techniques. Adoption of EUV will reduce the need for multi-patterning and, in effect, the need for EDA for that specific purpose. Therefore, companies like Synopsys (SNPS) and Mentor Graphics (OTCQB:MNTR) will be impacted by EUV adoption.

Foundries and x86?

Foundries like Taiwan Semiconductor Manufacturing Company (TSM), Samsung (OTC:SSNLF) and Global Foundries will be able to reduce costs using EUV for manufacturing at nodes like 7nm.

As node lead is important in x86 arena, anyone who has a node advantage will benefit from using EUV, as it will offset the cost disadvantage of being at a leading node. Therefore, node advantage will be the key competitive advantage for Advanced Micro Devices (AMD) or Intel (INTC) as cost disadvantage won’t come into play if EUV is introduced without double patterning.

Right now, it seems AMD will have the node advantage going forward.

Final Thoughts

There isn’t much clarity around the adoption of EUV. On one hand, ASML is claiming that 250W source gives EVA a cost advantage over conventional techniques. On the other hand, industry experts have their concerns about the use of double patterning as EUV won’t be enough at smaller nodes like 7nm and 5nm. Therefore, investors in the semiconductor industry should closely follow the developments in EUV arena.

A single exposure EUV implementation at 7nm will benefit companies like ASML, TSMC and AMD while creating headwinds for EDA and semiconductor manufacturing companies like Synopsys and Lam Research.

However, if double pattering is needed alongside EUV at 7nm, the cost advantage might not exist. This will adversely affect ASML and will put AMD at a cost disadvantage as compared to Intel at 10nm. EDA companies will also benefit amid the need for more patterning leading to more design automation services.

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