Micron And Intel: Fishy?

Apr. 05, 2019 7:50 PM ETIntel Corporation (INTC), MU764 Comments96 Likes

Summary

  • I've tried to avoid the topic of "the ECD bankruptcy" as it relates it Micron and Intel.
  • Unavoidably, it needs to be revisited.  Don the tinfoil.
  • There is no possible bad outcome for Micron and Intel.

You can probably skip this section if you've been following along for the past few years now. This is just a recap on the ECD story. But it's a good story.

A Long Time Ago, In A Land Far Away...

More than seven long years ago, a company by the name of Energy Conversion Devices ("ECD") declared bankruptcy after 50 years of crazed, prolific invention. With respect to its founder, Stanford Ovshinsky, Scientific American recently wrote an article entitled The Most Important Inventor You've Never Heard Of, which is worth a read if you need to bring yourself up to speed on the company.

I still hold the bankrupt ENERQ shares in the company with hope that they will pay out someday. This situation is now finally in front of the judge and may wrap up any day. It's described formally (but heavily redacted) here. It's alleged that Micron (NASDAQ:MU) and Intel (NASDAQ:INTC), among other individuals, were involved in a conspiracy to misappropriate what we now know as 3D XPoint/Optane, or more generically as phase change memory ("PCM").

For those of you who have been along for this ride, you certainly know that I believe that it was misappropriated. Back in 2009, I invested heavily in ECD after Intel and Micron told us that stackable ("3D"), transistor-less PCM and Ovonic switches ("PCMS") would be game-changing technologies. They did not keep it a secret and would go on at length as to how it was going to change the world. But then ECD, despite a high cash position, suddenly declared bankruptcy and Micron ended up with all of the intellectual property.

Like climatology, I don't have any expertise on chip technology so I just listen to what the experts tell me. So don't criticize me for repeating the informed opinion of the collective experts. When Intel and Micron said that this stuff was going to change the world, I believed them. And I thought that it smelled fishy when they ended up with the IP at artificial fire sale prices (the ECD bankruptcy wasn't necessary since they had plenty of cash to mothball their very profitable UniSolar subsidiary until economic recovery). This was reinforced by the fact that Micron and Intel suddenly went dark on talking about how PCMS was going to change the world.

Fishy.

So I wrote a manifesto back in 2015 to expose what I believed to be an injustice. And sure enough, a month later Micron and Intel gave journalists less than a week's notice on the formal but clumsy 3D XPoint announcement, which also smelled fishy to everyone else. In hindsight, it appears that they rushed this introduction so that they could deny that it was Ovshinsky's PCM technology, which they knew was a lie.

This was very brazen of them.

But when the ghost of ECD didn't go away, Micron and Intel delayed the technology and its scope of changing the world. But ECD still didn't go away. So Micron and Intel finally gave into the game of chicken and shipped a heavily-sandbagged Optane product in April 2017. That chip was quickly torn down and inspected by the experts, only to find the terrible lie inside - phase change memory and Ovonic switches ("PCMS").

Pockets Full of Sand

When I say that the chip is sandbagged, just know that you don't need to be a weatherman to know which way the wind blows. This is a cross section taken of a typical processor (this particular one is a 14 nanometer Intel processor):

Intel 14nm Cross Section

Source: TechInsights / ChipWorks ©2014

Using only hobbyist levels of observation, you can see a total of 28 tiny (click to zoom) transistor fins (a la FinFET) at the bottom layer of the chip. The slightly lighter colored layer above those is a layer of transistor control gates. This layer appears contiguous because the transistors are packed in so tightly in the third dimension that cannot be seen in this cross section. Just know that behind those 28 transistors that you can see, there are billions (literally) of other transistors.

In any event, above the transistors are layers of increasingly coarse metalization - just wiring which not only connects the transistors in the complex patterns that are required for computing, but also grows to the scale required to interface the chip with the outside world. A chip is no good if you can't get data in and out of it. This is what a normal CMOS chip (think processor types - CPU and GPU) looks like.

All processor makers like Apple, (AAPL), AMD (AMD), Nvidia (NVDA), TSMC (TSM), Samsung (OTC:SSNLF), Qualcomm (QCOM), Broadcom (AVGO), TXN (TXN), Google (GOOG) (GOOGL) and the others use traditional CMOS fabs. The distinction that I'm trying to paint is that CMOS is fundamentally incompatible with memory fabs, which leverage non-CMOS gear in order to emphasize the different characteristics required for DRAM and flash memory. This is the reason that processor and memory have never been combined at scale on any chip including memory chips (with very bulky SRAM being the only CMOS-compatible, energy-efficient memory). There's a pretty good outline of these differences over at StackExchange and further detail at SemanticScholar.

Now take a look at a similar cross section from an Optane chip:

Fishy Optane Source: TechInsights ©2017 with annotations by Stephen Breezy

First of all, I've put the cart-before-the-horse on some terminology: FEOL and BEOL stand for front end of line and back end of line, respectively. They are just distinct locations in any given chip fab. To simplify, you process silicon to make the transistors on the front end and everything else on the back end. There's a distinction because all of the sexy technology was historically deployed on the front end.

But with 3D technologies such as 3D XPoint, we're now able to make sexy stuff above the silicon, as is clearly evident here. In the case of this particular Optane chip, the second half of the back end is the sexiest part of this chip (no pun intended).

And that is the fishy part.

You see, back in 2009, Intel told us that one of the most desirable features of PCMS was its "CMOS compatibility" - the ability to be fabbed by the same equipment that's used to make regular processors (again, CPUs, GPUs and the like).

You can see the dichotomy in the Optane cross section above. Most of the chip is built on a very old Micron DRAM process. This is likely their prototyping test mule that they used to develop the technology. The interesting part is that the Optane layers - built with traditional CMOS - would appear to be much more at home at the bottom of the Intel 14nm chip at the top of this article.

Given the compatibility of thin-film PCMS with mainstream metallization schemes, multiple layers of cross point memory arrays are feasible. Also, this back-end technology is fully stackable over CMOS circuits to achieve excellent array-efficiency and reduced die size.

...

The Ovonic Threshold Switch enables area efficient memory layout and possesses compatible scaling attributes with PCM for future random access memory and solid state storage applications. Integrated with CMOS, PCMS provides the most promising NVM technology in scalability.

-Kau, Derchang, Intel Corporation, Numonyx B.V., et al, A stackable cross point Phase Change Memory

Summary

The tape-out date on the current Optane chips is from 2014 so we know that there is much, much better technology coming. And we know that they're running on crusty DDR technology, which limits speed to the hundreds of megahertz instead of the gigahertz where it should be. The wafers were first processed in a DRAM fab for the front end and most of the back end. But then they were moved to a CMOS fab where the 3D XPoint was added. These are handmade chips - not the droids that we're looking for.

Curiously, Intel raised the memory addressing limits of their forthcoming Sunny Cove architecture because 256 terabytes - a limit that isn't even scratched today - apparently wasn't big enough for them in the near term. Sunny Cove will support 4 petabytes of memory. That should be a big hint as to what's coming.

Optane chips are large for no reason. The silicon which sits beneath them is largely empty space - just some encoding, decoding and error control. Boring DRAM stuff. There's no sexy silicon where there should be - compression, encryption, etc. But - most importantly, a processor needs to be down there. And the whole chip needs to be fabbed with gigahertz-capable CMOS. Lastly, there needs to be another 15 layers of memory on top of this one. At least.

All at 10 nanometers. Terabytes stacked on top of the CPU and GPU. All of it will be accessible in a fraction of a second.

Game changer.

Memory access latencies are some of the major limitations on data -intensive computation performance nowadays. The possibly achievable CPU clock frequencies must be limited to the maximum access speed of the off-chip memory which constrains the overall system speed, regardless of the power consumption constraints. This computational bottleneck is commonly referred to as the Von-Neumann bottleneck. Memory access latencies can be drastically decreased by integrating the main memory onto the CPU. Phase change memory ("PCM") provides the possibility of integration of high-density highspeed non-volatile memory banks on top of the CMOS layer. This computer-on-chip concept has the potential to achieve up to 3-4 orders of magnitude of improvement in computation speed depending on the application. The performance of this computer-on chip system can be further improved by having the ability to perform logic operations in the memory layer which will also relieve and better utilize the underneath CMOS real estate.

- Kanan, Nadim H., Phase Change Devices for Nonvolatile Logic (2017). Doctoral Dissertations. 1371.

Conclusion

The ECD bankruptcy trust just filed a document which states that they expect their efforts to sell an AI subsidiary to "continue through 2019." It doesn't matter if Micron and Intel misappropriated the technology or not - ECD is gone and it isn't coming back. Micron and Intel now own a da Vinci (Ovshinsky?) that gives them a leg up on nearly half a trillion in total annual market. I suspect that this is what is behind the hold up on 3D XPoint gen2 and Intel's 5G, Cannonlake, and silicon photonics, among other things.

It really doesn't matter what it costs. Just realize that we won't see the real non-silicon breakthroughs until ECD finally wraps up. Now that it's in the sunlight in front of a judge, I think that Micron and/or Intel will just settle this amicably so that they can finally release these technologies. Maybe they'll drag it through the court for another year.

But it seems clear to me now that ECD is the cause for all of the delays at Micron and Intel. However, I'm all ears on other informed opinions.

This article was written by

“I shall be obliged to write just as if I were considering a topic that no one had dealt with before me” (AT XI 328, CSM I 328).
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Disclosure: I am/we are long MU. I wrote this article myself, and it expresses my own opinions. I am not receiving compensation for it (other than from Seeking Alpha). I have no business relationship with any company whose stock is mentioned in this article.

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