Dead are all the Gods: now do we desire the overman to live. - Friedrich Nietzsche
In The Gay Science, Friedrich Nietzsche attempted to explain the loss of objective morality associated with specific religion - namely Christianity. Still extremely controversial, Nietzsche's philosophy, which could be categorized as "atheistic existentialism," stands in sharp contrast to "Christian existentialism," a philosophy popularized by Søren Kierkegaard.
Well, what's wrong with the loss of objective morality? Who cares if society's modus operandi is subjective morality? C.S. Lewis attempts an explanation, saying that:
In a sort of ghastly simplicity we remove the organ [chest, or heart, referring to morality] and demand the function. We make men without chests and expect of them virtue and enterprise. We laugh at honour and are shocked to find traitors in our midst. We castrate and bid the geldings be fruitful. - C.S. Lewis, The Abolition of Man
The obvious issue examined by Lewis is that a decadent society will eventually collapse, and in an odd way, the semiconductor industry is in a similar predicament.
Moore's Law, which is an observation made by Intel (INTC) co-founder Gordon Moore where the number of transistors on a chip doubles every year while the costs are halved, seems dead.
Fortunately, for consumers and electronics lovers, my silly analogy between western culture and the semiconductor industry quickly disintegrates at Moore's Law's death, because there are possible solutions to try to eke out a few more years of semiconductor performance improvement, one of which is Atomera's (NASDAQ:ATOM) Mears Silicon Technology. In this article, I will discuss the immense value proposition for Mears Silicon Technology, and possible catalysts for the stock.
Atomera Incorporated is a semiconductor materials and intellectual property licensing company actively working to deploy its proprietary technology, Mears Silicon Technology (MST), in the multi-billion-dollar semiconductor industry. MST claims to increase performance and power efficiency in semiconductor transistors. As Moore's Law becomes increasingly questionable, MST becomes increasingly valuable.
The semiconductor industry has made huge strides for decades on end, allowing for a plethora of previously unfathomable industrial and social advances throughout the world. These advances are backed by an underlying improvement in the data and computer hardware that we use. Many of these pieces of hardware, such as RAM, processors, and solid state drives, are made from microscopic circuits of transistors. Moore's Law is an observation by Intel co-founder Gordon Moore stating that the number of transistors on a chip (and therefore computing power), an integrated circuit, doubles roughly every two years while the costs of production are reduced. In the past, new software products could be designed for the future, knowing that the improvement in hardware would emerge as those products were launched. Vice-versa was also the case, as Intel could be confident that there would always be a demand for their new and improved chips.
Basically, the whole industry used Moore's Law to predict technological advances and to plan to be able to utilize them . This enabled rapid growth, creating an over $400 billion semiconductor industry. However, uncertainty regarding the continuing performance increases and cost decreases due to, for instance, quantum effects, question the future validity of the Law. As the low hanging fruit of transistor shrinkage comes to an end, other creative semiconductor improvement solutions are needed.
What Is a Transistor?
Before discussing the merits of creative semiconductor improvement solutions such as Mears Silicon Technology, the basic architecture of a transistor, the fundamental unit in a chip, must be understood. A transistor is a device can either conduct (or not conduct) electrical current. It can act as a switch and an amplifier; these traits make it extremely useful as the basis for modern day computers. Below is a video that can bring readers who are not familiar with semiconductors or electrical engineering up to speed with transistors. There are many different transistor designs, but the basic principles remain the same.
Click on this video link if you are not familiar with transistors.
Basically, to make a chip in traditional semiconductor manufacturing, many transistors are etched onto a base and connected by conductors on the emitters and collectors. A high enough voltage across the base leads to crowding of electrons on the one side of the base, forcing electrons into the conduction band. The electricity can flow through the base if it has an electric field through it, allowing the electrons to more easily move through higher bands (conductance bands) in the semiconductor (usually silicon, which has a small band gap) material. Nowadays, billions of these are organized into circuits that comprise what we know as processors, RAM, and even solid-state hard drives. So, over time, the circuits have shrunk and more and more complex and efficient circuitry has been fitted into smaller and smaller chips. However, the physical limitations of simply shrinking circuits via geometry and advanced manufacturing capabilities are approaching and becoming increasingly apparent. Now, people have been saying this for years, and there will be solutions developed. However, let's take a look at some of the limitations to simply continuing to shrink silicon-based transistors.
For years, people have predicted the end of Moore's law, yet these projections for a Moore's law breakdown keep getting pushed out due to innovative solutions. Some sample problems (depending on the application) include:
Manufacturing With Extreme Ultraviolet Lithography (EUVL)
EUV manufacturing lends itself to issues called stochastic defects, a problem the semiconductor industry is still working through. These defects are random, isolated, and non-repeating, which makes them hard to find and troubleshoot. They also can cause chip failure. Basically, there is variation at smaller sizes and practical difficulty in measuring those variations. An example of a stochastic manufacturing failure is the microbridge, or "locally broken lines and missing or merging contacts", shown in the picture below:
Another issue with chip design, at around 5nm or below, is quantum tunneling. Electrons' location is essentially a probability function (see the Schrödinger equation), so electrons can cross physical barriers and therefore leak across the gate as well as in other areas. In the past, these issues were solved by using a high-K (dielectric constant) gate to increase gate thickness without changing the overall permittivity of the dielectric . However, as transistors shrink, these dielectrics simply don't work anymore as their thickness also shrinks proportionally to the rest of the chip's components.
Moore's Second Law (Rock's Law)
As the price, or consumer costs, of computing power continue to fall, the capital required to fulfill Moore's Law increases. R&D, manufacturing, and test costs continue to increase at a rapid rate, as seen in the graph below, which describes design costs at each node.
Last year, the CEO of International Business Strategies, Handel Jones, stated that:
3nm will cost $4 billion to $5 billion in process development, and the fab cost for 40,000 wafers per month will be $15 billion to $20 billion.
Clearly, there are higher costs associated with moving to smaller and smaller nodes.
The important takeaway is that there comes a point at which many solutions for improving transistor design are at the point of diminishing returns, where the improvements become more costly and the returns shrink somewhat due to various problems. Obviously, the end of innovation on this front is somewhat of a moving goal post (moving dead end), but in this case, the clearest solution insight might be Mears Silicon Technology; it is relatively inexpensive to implement and has obvious benefits to any virtually any existing silicon-based design.
When Will Moore's Law End?
For years, it has been speculated that costs will rise and benefits of shrinking will diminish, signaling the practical end of Moore's law. According to Paul Penzes, Vice President of Engineering at Qualcomm (QCOM):
Speed gains of 16% at 10 nm may dry up at 7 nm due to resistance in metal lines. Power savings will shrink from 30% at 10 nm to 10-25% at 7 nm, and area shrinks may decline from 37% at 10 nm to 20-30% at 7 nm.
As such, in order to increase computing power, manufacturers may simply change the architecture of their chips in order to stack more layers of circuitry, for example.
Regardless, even if size diminishes, the cost and power improvements seem to be somewhat asymptotic, so unless the bleeding edge manufacturers move to graphene or another material, improvements in power consumption and computing power will have to come from other sources at some point rather than shrinking transistors. Therefore, inexpensive turnkey solutions for the vast majority of silicon chip manufacturers should be in demand.
Mears Silicon Technology is a single-layer oxygen layer superimposed in silicon - a superlattice, which allows for lower power consumption and chip size, as well as reduced variability in manufacturing. Electronic Design, quoting Mears, helps to explain:
Robert Mears, founder of Mears [Silicon] Technology, describes his company's MST technology for CMOS as one that makes relatively simple changes to silicon. 'We can modify its properties so that it becomes inherently anisotropic,' explains Mears. 'As a result, it becomes more conductive in the plane and less conductive out to the plane.'
MST technology involves a film that acts as a channel-replacement technology, sitting directly below the gate dielectric. This film's anisotropic properties enhance current flow from source to drain, providing higher mobility so ID sat (saturated drain current) is improved and drive current is higher. At the same time, the gate leakage is reduced without increasing the thickness of the gate oxide.
Mears Silicon Technology Was Invented Years Ago: Why Isn't It Already In Use?
Moore's law wasn't close to ending, years ago. Incremental changes in design have allowed Moore's law to continue a bit past where some people thought it would stop. However, there are significant costs (i.e. Moore's Second Law) and significant physics (i.e. quantum tunneling) and manufacturing (i.e. EUV lithography) issues associated with continued shrinkage of transistors, at least on silicon. But now, because the relative cost of MST compared to these other alternatives has shrunk, MST is ripe for the picking.
Also, there is now a focus on power efficiency, as chip sizes are so small already and battery usage in mobile devices is a customer focus and selling point. MST can offer very large improvement in battery usage when incorporated into chip design.
Technological Benefits of Mears Silicon Technology
There are a number of benefits of MST in various applications, so depending on the type of semiconductor, there may be different, more, or fewer reasons to use MST. Regardless, MST is beneficial across the board of transistors.
Reducing Threshold Voltage Variance, Dopant Diffusion Containment
Reduces transistor threshold voltage (Vt) variation by blocking transient enhanced diffusion (TED), diffusion of the dopant, which is usually boron or phosphorus, during the annealing process [2,3]. This can result in a shallower junction depth as well as general quality control.
When dopants are added to silicon, the resultant crystalline structure is disrupted, and the material requires annealing. The intended result is for interstitials to recombine with vacancies. Most of the interstitials recombine with vacancies during annealing; however, some of the dopant concentrates near the surface. These concentrations result in leakage and threshold voltage variance, meaning poorer performance and poorer manufacturing control, respectively. As seen below, TED and these surface concentrations are what MST helps control during manufacturing.
The manufacturing control importance is greater than one might think:
Variability is a big deal to designers, because they have to design circuits to work with the worst-performing devices even though there may be many neighboring devices that are much speedier or more power efficient. As transistors shrink, one big source of variability is the number of dopant atoms in a given area. For large transistors this is less of a problem, because they contain thousands of dopant atoms. But small transistors might have only a few hundred. So 10 atoms more here or 20 fewer there will have a noticeable difference in the device's abilities. (See " The Threat of Semiconductor Variability," IEEE Spectrum, July 2012 for a better view of this problem.)
According to Mears, customers have seen 20 and 40 percent improvements in matching, which attests to MST's variability control. The steep dopant profile shown in the slide above keeps more dopant away from the dielectric surface, which is thought to be the cause of some aging effects.
There are various forms of leakage in a transistor. The three major types are 1) gate leakage, 2) subthreshold leakage, and 3) reverse bias junction leakage. A more complete list of leakage sources is as follows:
(I1) Reverse Bias pn Junction Leakage Current
(I2) Sub-threshold Leakage Current
(I3) Drain-Induced Barrier-Lowering Effect
(I4) Gate Induced Drain Leakage current (GIDL)
(I6) Narrow-Channel Effects
(I7) Gate Oxide Tunneling leakage current
(I8) Hot-Carrier Injection
Mears Silicon Technology can help reduce various forms of leakage in different types of transistor designs. As an example, for a FinFET, the oxygen inserted layer (MST) can help optimize the punch-through stopper to reduce leakage [4,5,6,7]. This will simultaneously improve transistor drive current, minimizing on and off state leakage, and reducing 1/f noise. The benefits of MST to FinFET design have been discovered by Atomera and summarized in their investor presentation slide below. For detail, investors should review their academic publications.
In regular CMOS transistors, instead of improving the punch-through stopper as in a FinFET, the analogous halo implants on these transistors can be reduced or removed. The implants are also manufactured to prevent punch-through or reverse bias leakage.
When considering bleeding edge nodes, leakage, specifically gate leakage, increasingly becomes a quantum physics problem due to the size of the transistor. According to Mears:
Gate leakage is a quantum mechanical tunneling problem," says Mears. In terms of electron tunneling, the gate oxide can be seen as a barrier. The ability of electrons to transgress that barrier can likewise be thought of in terms of an impedance-matching issue. MST technology effectively creates a mismatch that prevents electron tunneling without affecting the barrier's physical dimensions.
Leakage becomes more and more substantial with decreasing transistor size as seen in the figure above, and while some techniques such as dynamic Vdd (drain supply voltage) scaling, active cooling, and on-chip gating are already used to manage power consumption, any power consumption reduction is welcomed, as well as a reduction in subthreshold current and other forms of leakage.
Resistance Reduction / Power Reduction
The decrease in resistance or decrease in power usage from MST really comes from two sources: leakage reduction and electron mobility increase. MST has been shown to substantially increase electron mobility in the MST plane, and reduce mobility orthogonally. Electron mobility is also dependent upon temperature and impurities, but more simply, it directly affects drift velocity, which is directly proportional to current. Below is an explanation of the mobility increases seen with the band gap widening associated with MST, at the SiO monolayer interface.
So, the "improvement in mobility" seen in MST essentially reflects an ability to increase current or reduce resistance. Recently, Atomera demonstrated an up to 50% improvement in channel-on resistance in 5V NMOS analog switches by increasing mobility (from less distant quantum confinement/kind of like a planar Coulomb blockade) and some doping profile engineering. It should also be noted that this improvement is also due to quasi-confinement due to increased hole mobility separation of sub-band wavefunctions.
MST Technological Benefit Summary
Depending on the customer, Atomera can use MST for different semiconductor technological improvements. Bibaud states that:
today, due to the massive expenditures required only three top semiconductor players continue to develop the latest bleeding edge semiconductor process technology.
So, for older nodes, Atomera can stick with shrinking die size or power reduction. These nodes are becoming stickier, as Bibaud explains:
People are saying 28-nanometer will be useful for many years. And 40-nanometer chips are big in the world of automotive chips and for the Internet of Things. We've even heard that the 130-nanometer node has the newest design starts of any node today for things like analog and sensor and power applications.
Not all semiconductor manufacturers are going to the 7nm and 5nm new territory. There are separate markets for MST. Bibaud elaborates:
There are three ways MST can solve Moore's Law. For legacy nodes for analog and power devices, such as 180-, 130- and 90-nanometer, they can shrink their die size while getting the same performance. At 65-, 40- and 28-nanometer MST can give a new level of performance and lower power at the same node, allowing fabs to be productive longer. And at very advanced node like 16-, 14- and 10-nanometers, FinFETs using MST will allow fabs to continue using bulk silicon rather than going to other materials like III-V channels.
This is truly quite interesting - one process improvement will help different semiconductor fabs in different ways. Investors can analyze other benefits and technical details of MST in the "publications" page on Atomera's website. Now, the technical improvements gained from MST implementation alone don't justify an investment from a fab. However, MST is easy to implement in existing mainstream semiconductor fabrication processes.
Perhaps the biggest benefit of MST is that it is easy to implement into existing manufacturing processes. For manufacturing, many fabs still use silicon epitaxy. The idea is, essentially, that silicon crystalline growth would be stopped, and oxygen would be allowed to briefly grow on the silicon, and then the silicon would continue to grow. Basically, it requires a few extra but simple steps using standard equipment. All of this can be done for "tens of millions" of dollars, instead of spending over a billion for a process shrink.
Atomera was founded by Robert Mears, who notably was involved in the invention of the Erbium-doped fiber amplifier, a key innovation which allows amplification of fiber optics so that they can be wired at longer distances. Needless to say, Mears and his team have much experience in device and material innovation in the electronics field.
The rest of the management team has considerable experience in the semiconductor industry, including CEO Scott Bibaud, who led a highly successful and hasty turnaround of one of Broadcom's money-losing divisions. He previously grew Broadcom's Bluetooth segment from $0 to $650 million in revenue, the worldwide market leading position, with significant operating profitability. Overall, Atomera's management team appears experienced and well-equipped to tackle an industry-wide integration of MST.
Atomera currently has minimal revenues; the revenues they are generating reflect the engineering consulting fees companies pay them to do preliminary work with MST on their chips. In addition, Atomera probably has about $20 million in cash after their recent stock offering pretty much at market price, with a ~$3 million per quarter cash burn. While Atomera may need to raise money again at some point, they may be very close to finalizing some sort of agreement with STMicroelectronics (STM) or AKM Semiconductor:
Based on only about a week of discussions with customers, I also anticipate a rapid expansion of our pipeline over the coming quarters. Exiting this quarter, we're up to 22 customer engagements with 17 different customers, representing at least 50% of the industry's largest players. Our two licensees, ST and AKM, continue to run wafers with us and make progress towards their ultimate production goals.
While speculative, clearly companies are interested in implementing MST to their fabrication process; otherwise, they would not be paying Atomera engineering fees. Atomera's new strategy of filtering out the customers who don't want to pay engineering fees - so that they focus their time and resources on those who do - is an excellent method of prioritizing business development and sales, and investors should view this as extremely bullish for the company, along with their recent demonstration of a 50% improvement in on-resistance for 5V NMOS. Atomera's game has heated up substantially within the last few months.
Thus, as a catalyst, expect Atomera to be able to ink a deal or two in the near future and become cash flow positive. A possible license deal could include an upfront payment of a few million and recurring royalties up to possibly 7%, providing Atomera a TAM of up to $28 billion. The true TAM remains to be seen.
The biggest risk investors take with Atomera is the fact that they are a pre-revenue company. If they don't reach a manufacturing deal with a substantially sized fabricator, expect more dilution. Also, it will take about a year for a deal to turn into recurring royalty revenues, likely based on average selling price.
Other risks include a possible transition of the semiconductor industry away from transistor, electron-based data storage like NAND flash, to phase-based data storage such as 3D XPoint technology developed by Intel and Micron (MU). Yet another risk includes usage of different semiconductor materials such as Germanium; however, Mears Silicon Technology likely will be applicable to other materials such as Ge. Regarding next-generation materials in general, it seems Atomera has preliminary plans for offering improvements:
Our engineering team believes that the technologies underlying MST® can be part of a larger platform of reengineered materials beyond CMOS, including:
Faster and more efficient nano-structured semiconductor materials for electronic applications Enhanced nano-structured materials for application in photonics Improved magnetic materials for advanced memory
For the longer term future, the company also has improvement ideas for magnetic materials of next-generation advanced memories. These ideas are somewhat analogous to MST, although they are not developed at this time.
However, other solutions for extending Moore's Law are possible competition, although they may end up being synergistic solutions:
The bottom line is that besides a drastic change in memory manufacturing such as switching to III-V materials that might be incompatible with MST, phase change memory, or some combination approach, Mears Silicon Technology will likely be a great turnkey solution to improve most existing chips without making risky expenditures and large technological shifts.
Many semiconductor companies will not be pursuing non-transistor based chips in the foreseeable future. For these companies, implementing MST could be a way to substantially improve products without spending billions on a fab upgrade. For those manufacturers on the bleeding edge, MST might be the best financially feasible or risk-averse improvement to, for example, FinFET chips.
Maybe if you define Moore's Law as simply the number of transistors in a given space, the law isn't dead. But power consumption and leakage are essential aspects to improve on, and Mears Silicon Technology could play a large role in improving these aspects. And, if power consumption can be improved, so can computing performance.
In some ways, going long ATOM is like buying a hedge against the semiconductor industry (without selling anything short), as Atomera will accelerate testing and implementation with customers as temporary periods of oversupply allow time for equipment (fab) downtime. So you can speculate that when the semiconductor industry lulls, Atomera will be making progress. While there are other improvements coming to semiconductor design, Atomera is targeting a large portion of the industry that is not engaging in cutting edge semiconductor improvement and would benefit from an effective turnkey solution without sacrificing much more in capital equipment upgrades. Investors in Intel, STM, Micron, TSMC (TSM), Samsung (OTCPK:SSNNF), Texas Instruments (TXN), or NXP (NXP), etcetera should look into Atomera as a possible hedge to their portfolios; when demand slows, Atomera is making progress. Other small cap investors should do more research on Atomera as a stand-alone investment as it has enormous potential, strong management, promising technology, and clear demand.
There is no telling how quickly Atomera will be able to capitalize on its technology, but it is conceivable that Atomera will be able to pick up a customer or two within the next year and become cash flow positive. If they don't execute quickly enough, dilution could be around the corner. However, if an order or two come through, the floodgates may open. Investors won't want to miss that. The scientific evidence presented looks compelling, demand for solutions such as MST is clear, and management has a good history of success. This bodes well for a company whose total addressable market completely dwarfs their market cap.
Disco, Cornelius; van der Meulen, Barend (1998). Getting new technologies together. New York: Walter de Gruyter, p. 206-208.
Special thanks to Tailwinds Research for this investment idea.
This article was written by
Disclosure: I am/we are long ATOM, MU. I wrote this article myself, and it expresses my own opinions. I am not receiving compensation for it (other than from Seeking Alpha). I have no business relationship with any company whose stock is mentioned in this article.