- Given AMD's Xilinx acquisition, questions arise about who will hold FPGA leadership going forward.
- Intel Agilex FPGA achieves 30-50% higher performance and 2x performance per watt than Xilinx Versal.
- Intel further leads in innovation due to leadership transceivers, chiplet and 3D packaging, and AI performance.
- This means there is one clear winner. Intel is the unquestioned leader in FPGAs. Xilinx-AMD could be in trouble.
With AMD (NASDAQ:AMD) acquiring Xilinx (XLNX), the multi-decade competition with Intel (NASDAQ:INTC) will continue in FPGAs going forward. While not a segment that is as closely followed (as no one has an FPGA in their PC), naturally the same question arises: who has FPGA leadership?
I reviewed the Ice Lake-SP launch a while ago, but the unsung hero of that event actually was Intel's Agilex FPGA launch. Long story short, Intel drove home the point that it is the unquestioned leader in FPGAs. If Intel can translate this into market share gains (admittedly there is no evidence of this yet, but this may be partly due to the shortages), then Xilinx and hence AMD (investors) could be in deep trouble.
Longer term, an even bigger risk for AMD and Xilinx is Intel's next-gen FPGA, as it appears this will feature a breakthrough architecture that could offer unprecedented advances due to Intel's packaging leadership, further increasing Intel's leadership.
Additionally, in my recent analysis of Intel vs. AMD, some readers noted that I had not discussed FPGAs. This will be addressed here.
What are FPGAs?
In brief, an FPGA is (as the name implies) a programmable logic device. This is best explained by comparing it to other kinds of chips: whereas a CPU is fully programmable through software, and in an ASIC a specific algorithm is fully baked in hardware, an FPGA can be "programmed" at the logic (boolean) level. This means the logic will be tailored to the algorithm (like an ASIC), but can be changed (reprogrammed) to cater to different algorithms. This results in speed, flexibility and efficiency characteristics in between fixed-function chips and CPUs.
Leading edge FPGAs additionally pack quite a bit of computational power through DSPs, rivaling GPUs in fact. Given the rise of AI, both Intel and Xilinx have further added reduced precision support (such as INT8) and in some FPGAs even matrix engines (in analogy to Nvidia's (NVDA) Tensor Cores).
(This shows that Nvidia's success in AI has been mainly due to its fast time to market in 2017 with the V100, resulting in a first-mover advantage: Xilinx and Intel (and many start-ups) have shown that Tensor Cores can be added to other chips than GPUs and deliver rivaling or even superior performance.)
Regarding Xilinx-AMD, I analyzed the acquisition when the first rumor popped up: AMD To Acquire Xilinx: The Imitation Games Continue. The final announcement of the acquisition, which will close by the end of the year, has changed little to the narrative.
As a recap, the synergies of CPUs and FPGAs are known from Intel's acquisition half a decade ago: an FPGA can be used as a data center accelerator, as an AI accelerator, as a SmartNIC, and as an accelerator in network infrastructure. Although I also noted these synergies have not resulted in much growth to date for Intel's FPGA (programmable solutions group) business. While (the standalone) Xilinx may have done a bit better, its financials, too, have been mixed.
As one addition to this discussion, the following question was asked on the call at the time and might be worth quoting in full since I have seen many AMD bulls who argue that AMD's acquisition is supposedly different than Intel's; I will argue it isn't.
So my Xilinx question, so I gave a CPU company buying an FPGA somebody obviously has been tried before your competitor tried this as well. It was not terribly successful to the point. How would you say your vision for what you can do with Xilinx is different, maybe from what Intel might have a view with Altera? And maybe what lessons have you potentially learned from the issues that they've had with that deal?
Yes absolutely, Stacy, I'll make a few comments and then, I'm sure Victor will have a few comments. Look, we've been thinking about this for some time and I think it's actually a very different situation Xilinx is the market leader. I mean if you look at how their business has grown over the last few years. Their market share has continued to grow. I think both companies are executing really well.
So you ask why now I mean, why now is actually we feel very good about our base businesses. I think the people look at our businesses and say they're complementary and they are very complementary from a product and market standpoint. But we have sort of important intersections around the data center focus and then also around the technology sort of strategy, right.
I mean where we're both leading-edge technology users. We both have partnered with TSMC. We both have really leaned into this modular design environment and Xilinx is a leader in some of that - some of the 2.5 3D integration. We’re both invested in software and open source. So there are a lot of synergies that are sort of under the covers that we see and we see very strongly. And I think you'll see as the road maps execute.
And then I think the last point I'll mention is, I think our cultures are very, very aligned and we're both Victor and I are both engineers at heart. We love the technology we have a common vision, I'm really, really happy that he is joining me on this journey. I think, we have a bold vision of what we think we can do for the industry and for our joint companies. And I think that's, that's what we see as the - what's different and as you know, Stacy.
I mean I haven't been big on M&A. We're not doing M&A for M&A sake. I mean this is such a unique opportunity there actually is no better match in the industry for us than Xilinx. So Victor, you want to add some comments.
Yes, I think you put it very well Lisa. I think this is completely different than that transaction. And I guess, I'll just lean into the fact that as Lisa said. We have very common vision for the transformations that are happening, not only in the data center. But I would say at the edge and even endpoint applications. And I’m super excited about joining back with AMD and with the Xilinx team.
And I think we really do have very similar cultures, very focused on innovating very focused on execution and strong teamwork culture for both within the company and also with customers. And I think this is what it's all about. We're going to create tremendous value for customers. And I'm really excited to bring some of the underlying technologies that Lisa talked about to the fore and you'll see that over time, so. Yes, and clearly, I personally I'm, all in so. We’ll make sure that we integrate well.
To elaborate, describing the Altera acquisition as unsuccessful is misleading at best. Contrary to what the AMD and Xilinx managements would like investors to believe, the Intel + Altera combination is exactly the same as AMD + Xilinx: take a CPU, and add an FPGA. Then either (1) put it in the data center as an accelerator or a SmartNIC for offloading, and/or (2) use it for a comprehensive network infrastructure portfolio, and/or (3) use it to pursue other edge opportunities.
That is the strategy to which Intel has executed its acquisition, and I don't see any difference in how AMD will approach the Xilinx acquisition: to expand its opportunities. Two more arguments:
- As far as technology is concerned, the synergies of Altera-Intel are actually much broader. Some may remember that Altera was Intel's first landmark foundry customer long before Intel Foundry Services. So Altera uses Intel's manufacturing, and additionally is also the leading user of Intel's industry-leading advanced chiplet packaging (with EMIB). Additionally, Intel's oneAPI software initiative also encompasses FPGAs, creating a unified and open programming model spanning CPUs, GPUs, FPGAs and NPUs.
- The go-to-market synergies as well as overall portfolio are also in favor of Intel: Intel has a leading position in (5G) network infrastructure as a whole, compared to AMD who is still mostly absent in this market. (Although AMD bulls have argued that this allows AMD to expand into new markets.) Intel further has an ASIC business and also acquired Easic for an even broader portfolio: Intel calls this the "logic continuum" from programmable to non-programmable silicon.
So although some of the synergies remain to be seen, as I outlined in the previous analysis in October 2020, the acquisition is indicative of and in line with AMD pursuing further growth given its nearly ~$200 billion market valuation, not unlike Nvidia's Arm acquisition. Nevertheless, contrary to the management quotes above ("this is completely different"), the acquisition is the same as Intel's one in 2015-2016, which means AMD is at least half a decade behind Intel in pursuing a synergetic CPU + FPGA strategy.
Does CPU-FPGA integration make sense?
There is one more topic with regards to the Xilinx acquisition that may be addressed. In particular, some investors seem to have the impression that AMD in the future will launch something like a super-APU which besides a CPU (and perhaps GPU) will also have an integrated FPGA.
Since AMD primarily serves two markets, let's discuss those individually. First, in the PC market the chance of AMD launching an FPGA are slim. As I have discussed previously, CPUs (especially Intel's) already contain many accelerators, but there does not seem to be a value proposition for FPGAs. Of course, perhaps AMD could try it and maybe this could create a new market, but in the more likely scenario that it would largely remain unused, then an FPGA would only add cost to the CPU.
Secondly, the more promising market for FPGAs (as indicated above) is the data center. However, it turns out that here, too, integrating an FPGA into the CPU is not necessary.
The reason for this is exactly the same as why GPUs in the data center are not integrated and why Nvidia has amassed an ~$800B market cap based solely on GPUs: an accelerator like a GPU or FPGA can simply be attached to the CPU through a standard PCIe interconnect link.
Of course, some may argue that integration could result in some benefits such as cache coherency. However, exactly for this reason the industry is on the verge of adopting a new interconnect standard, called CXL (as proposed by Intel in 2019, and backed by the full industry including AMD, Xilinx and Arm).
So in conclusion, the main rationale for the Xilinx acquisition is not hardware integration, but should rather be seen (as argued in 2020) that AMD sought to expand its TAM by entering the FPGA market. Any synergies would be (1) on a higher level like sales (e.g. offering AMD CPU + Xilinx FPGA as a competitive offering to an Intel CPU + Altera FPGA combination), and (2) software integration like how Intel has created a unified programming model through oneAPI.
FPGA developments: what happened previously
This section will summarize the key market trends in FPGA over the last several years. In particular, although Intel's financials don't show it, there has actually already been a clear evolution as to who will have FPGA leadership going forward.
Summing up the Altera-Intel developments:
- Due to pre-acquisition delays, Altera was one year behind Xilinx in moving to the 14/16nm node.
- However, Intel moved quickly and immediately invested in a parallel development team, working on 10nm Agilex well before the 14nm Stratix 10 even started sampling. As a result, Agilex and Versal started sampling around the same time in mid-2019. This means Intel moved to process technology parity in just one generation.
- Altera has been a highly successful Intel foundry customer. Altera is leveraging both Intel's leading processes as well as Intel's leading 2.5D and 3D chiplet packaging technologies, which has resulted in a rich chiplet ecosystem. Note that this was long before AMD even launched its first MCP (multi-chip package) ("Naples", 2017) into the market, let alone AMD's first semi-chiplet design ("Rome", 2019). Hence, contrary to what AMD fans often state, the industry's first adopter of chiplets is actually Altera.
- As a result, Stratix 10 and Agilex are part of an ever-larger chiplet ecosystem of first-party and third-party chiplets. This actually remains the only real, cross-vendor and cross-foundry chiplet ecosystem in the industry. I called AMD's approach semi-chiplet since it is still based on the legacy MCP approach.
- To show what this has allowed Intel to accomplish: despite the mentioned pre-acquisition delay, Intel was still able to deliver the industry's first 16/14nm FPGAs with (1) integrated HBM, (2) 58G transceivers, and (3) PCIe 4.0.
- Intel also acquired eASIC in 2019, which creates eASICs. These provide a feature set (in terms of cost, time to market, power, performance, etc.) somewhere between ASICs and FPGAs. These eASICs can also be added to the Agilex FPGA as a chiplet.
- Intel in 2019 created the Network and Custom Logic to deliver on the network synergies mentioned above. While Intel has actually seen some revenue drops because of lower FPGA sales in networking, Intel has said that these sales were shifted from Intel FPGAs to Intel ASICs. More recently, Intel said that it has been unable to fulfill all orders due to the shortages: "DSG revenue was $486 million, down 3% year-over-year due to significant supply constraints. Demand continues to significantly exceed supply for FPGAs."
- Intel FPGAs are also a key part in Intel's heterogenous XPU strategy, which on the software side translates into support in Intel's oneAPI initiative.
- Intel's FPGAs are also aligned to its AI everywhere strategy, since Intel launched the 14nm Stratix 10 NX with Tensor Blocks a few years ago. FPGAs can beat GPUs by perhaps an order of magnitude in some workloads in efficiency.
On the Xilinx side:
- Xilinx is calling its Versal products APACs (adaptive compute acceleration platform) instead of FPGAs, to highlight the inclusion of further IP and accelerators (such as for 5G and AI), which broaden as well as enhance their use-cases beyond traditional FPGAs.
- These APACs could be seen as the monolithic equivalent of Intel's approach of adding further capabilities to its FPGAs via chiplets: Xilinx's 7nm Versal roadmap consists of no less than six product lines (of monolithic chips).
- Xilinx's equivalent of oneAPI is its Vitis software. But obviously this remains an FPGA-only solution, whereas oneAPI is targeted towards Intel's full silicon portfolio.
In general, both Altera (Intel) and Xilinx (AMD) have adopted a strategy to expand the use-cases of FPGAs by including dedicated engines for acceleration. However, both companies have done this in a different way: Altera has been able to adopt Intel's industry-leading advanced packaging to create a chiplet ecosystem, which allows each individual FPGA to be tailored to the customer's requirements, whereas Xilinx is following a traditional monolithic approach.
Altera's chiplet approach has been successful given the examples of being first to integrate 58G/112G transceivers, Arm cores and HBM into the FPGA: the benefit of chiplets is that once they are created, they can be added to the FPGA without having to tape-out a completely new chip, vastly improving time to market.
Lastly, since the Versal and Agilex FPGA launched basically around the same time, it should be observed that Intel's investments have allowed Altera to catch up in that regard.
Given that both companies' roadmaps are quite clear, a comparison can be made. One point to note here is that despite Intel and Xilinx moving to 10nm/7nm at the same time, Intel has actually been able to establish a clear leadership by virtue of architectural leadership.
At the 10nm/7nm generation, both companies are taking a somewhat similar but also divergent approach, as already indicated. While both companies are proliferating their line-ups with multiple SKUs, Xilinx seems to be taking a more specific approach for several segments it is targeting (such as edge, 5G and machine learning) with a wide range of Versal ACAPs. To that end, Xilinx is focusing more on integrating multiple accelerators around the FPGA platform, hence the name ACAP. Note that these are all monolithic chips.
The Agilex FPGAs, on the other hand, primarily focus heavily on improving the core FPGA fabric (with what Intel calls the HyperFlex 2 architecture), with claims of 40% higher performance (frequency) or 40% lower power. Agilex also introduces various new features: hardened bfloat16 AI data type support, improved DSP performance (but no dedicated AI acceleration yet), as well as 116G transceivers, PCIe 5.0, DDR5 and CXL in future variants (through new chiplets).
These developments mean that for pure FPGA applications (which don't use any of the accelerators), Agilex has a very clear and tangible FPGA leadership as an overall superior platform over Xilinx. This is indeed what Intel drove home as part of its Ice Lake-SP data center launch early in 2021 (comparisons against Versal):
- 50% higher video IP performance;
- 2x higher (fabric) performance per watt;
- 30% higher (fabric) performance.
The second main difference is that Intel continues its chiplet strategy: the base 10nm FPGA is the same, but an ecosystem of chiplets can be attached to customize the FPGA. This approach has material advantages for development cost, feature set (due to the customizable chiplet ecosystem), and time to market. For example, some of the features mentioned above, such as 116G transceivers, PCIe 5.0/CXL and HBM will only be available in the future as these technologies become available.
To be sure, this is an advantage of chiplets, not a deficit: 116G transceivers, DDR5 and PCIe 5.0 or CXL were not available yet when Agilex first started sampling in 2019, so essentially Intel's FPGAs are future-proofed because of this chiplet approach: Intel would just have to create a small chiplet with (for example) PCIe 5.0 support. By contrast, Versal FPGAs will never be able to receive PCIe 5.0 support unless Xilinx's goes through the expensive effort to create a new full-blown monolithic chip. Of course, Xilinx will never do this to add just one feature.
This essentially means that besides performance (as discussed above), Intel further wins on connectivity and I/O support, since Versal does not have 116G transceivers, DDR5, PCIe 5.0 or CXL 1.1 support.
What this also means, is that nothing in principle prevents a customer from adding a chiplet for what may be an accelerator in Xilinx Versal ACAP, which indeed is Intel's strategy through its custom logic continuum from ASIC to eASIC to FPGA. For example, Intel's data center adjacency revenue started to increase meaningfully (by several $100M) with the ramp of 5G ASICs in 2020, confirmed for example here: "Delivered Intel’s leading 5G ASICs generating substantial incremental annual revenue". This implies the real underlying financial picture may be more nuanced than just comparing Intel FPGA vs. Xilinx, since the revenue of Intel ASICs is unknown.
Summing up, Xilinx's ACAP approach may yield higher performance in specific workloads, but investors should at least equally be aware of Intel's overall broader portfolio through its ASICs and eASICs as well as chiplet ecosystem (which easily allows to add other accelerators and features). In fact, when it comes to pure general-purpose FPGA performance, Intel's Agilex seems to be the fastest FPGA by a wide margin given its optimized HyperFlex2 architecture (with up to 2x performance/watt as well as higher performance).
Future Intel innovations
In addition to FPGA power and performance leadership, Intel has some more innovations in the pipeline, which are likely to further increase its leadership going forward:
- Stratix 10 NX: Industry-first FPGA optimized for AI, delivering 15x higher performance.
- PCIe 6.0 and CXL 2.0 will come to Agilex at a later stage (via a new chiplet).
- Industry-first 224G transceivers, targeted at the next-gen (Intel 4) FPGAs.
- Intel 4 FPGA: using EMIB and Foveros 3D packaging (featuring Foveros), this could result in over an order of magnitude higher efficiency and density.
It is the next-gen FPGA in particular that makes it clear that Intel could anything but further extend its FPGA leadership, as its use of 3D stacking will be unmatched by Xilinx.
Stratix 10 NX
I discussed the Stratix 10 NX when it was announced in June 2020 (in conjunction with Cooper Lake Xeon Scalable). It is Intel's first AI-optimized FPGA, featuring AI Tensor Blocks: the traditional DSP units were exchanged for AI Tensor Blocks, which basically have 15x more (INT8-capable) compute units, for a corresponding 15x increase in performance. This makes them competitive with Nvidia GPUs:
Taking aim at Nvidia, Intel says its Stratix 10 NX device is up to 2.3X faster than Nvidia V100 GPUs for BERT batch processing, 9.5X faster in LSTM batch processing, and 3.8X faster in ResNet50 batch processing.
Another paper describes how it achieved 8x the performance and 10x the performance per watt compared to Nvidia's V100 on a real-world state-of-the-art text-to-speech workload. Given these numbers, this makes it likely competitive with Nvidia's 7nm Ampere as well. (The reason the comparisons aren't against the more recent A100 is because those workloads weren't available/optimized yet for the A100 at that time.)
Following slide shows how it leverages its chiplets methodology to 'construct' the Stratix 10 NX from its chiplet library.
For the 'compute' chiplet, this is Intel's fourth 14nm based FPGA fabric and includes the AI Tensor Blocks. The other fabrics are FPGAs with or without the quadcore Arm A53 CPU, as well as a high-density FPGA for the Stratix 10 GX 10M (although not discussed here, another leadership FPGA).
The rest of the FPGA is similar to the Stratix 10 MX:
- The interconnect chiplets feature 58G transceiver (SerDes) technology and PCIe 3.0.
- There are no memory or 'specialized' chiplets.
- For other 'custom chiplets', there is support for HBM (via Intel's open-source AIB protocol).
Via this methodology, the NX is the sixth Stratix 10 variant (each with multiple SKUs for further differentiation on performance and features). Such a proliferation simply would have been impossible without chiplets: for example the Stratix 10 DX introduced PCIe 4.0 and UPI support.
Overall, this design methodology improves cost (since verification happens at the chiplet level) and time to market (as each new variant can come to market as soon as the chiplets it is composed of are ready).
PCIe 6.0 and CXL 2.0
The general PCIe interconnect has been on an accelerated roadmap. After years of PCIe 3.0, the industry moved to PCIe 4.0 around 2019 and PCIe 5.0 in 2021. CXL is also supported on Agilex, as it's based on PCIe 5.0. PCIe 6.0 (around 2023/2024) will further keep up with this Moore's Law-like cadence.
Intel's roadmap for Agilex confirms PCIe 6.0 and next-gen CXL 2.0 support coming in the future to these FPGAs. This will also bring support for beyond-400G Ethernet.
Revolutionary FPGA: Intel 4 and Co-EMIB
Intel has disclosed that its next-gen FPGA will be built on Intel 4 and use Intel's next-gen 'Co-EMIB' packaging technology. This will only further extend Intel's advanced packaging leadership.
Co-EMIB is basically the combination of 2.5D EMIB and 3D Foveros: it will leverage Foveros for 3D stacking of the base die, while also continuing to use EMIB for attaching chiplets. This is similar to Intel's Ponte Vecchio Xe HPC GPU.
However, the 2020 slide above did not indicate the significance of FPGAs moving to 3D packaging. In contrast, at the previous 2018 architecture day, Intel had hinted that it could use Foveros for stacking quite a bit more than just two layers (as it does in Lakefield and Ponte Vecchio). This would transform the FPGA into a "sea of configurable sectors". Intel indicated that this would bring as much as a staggering 1-2 orders of magnitude improvement in power efficiency. In other words, this could be a paradigm shift for FPGAs. WikiChip:
Looking a little further ahead, Intel also has plans to use Foveros for FPGAs. Intel’s next-generation FPGAs will make heavy use of chip stacking. The company expects Foveros to enable 1 or even 2 order of magnitudes increase in terms of performance, energy efficiency, or density compaction. The improvement comes from an entirely different way of configuring the FPGAs. To feed the high-end FPGAs today, the industry uses high-bandwidth memory which is connected through wires across all the configurable blocks. “With Foveros and 3D stacking, all of a sudden, you now have a sea of reconfigurable cores,” says Ravi Kuppuswamy, VP and GM of Intel’s Programmable Solutions Engineering Group. The major simplification comes from their ability to convert the traditionally long wires to short vertical ones.
224G Transceiver Leadership
Lastly, SerDes (transceivers) is likely a less broadly known technology component, but it is a quite important part of FPGAs, as FPGAs have multiple uses from storing to moving to processing data, which is where SerDes comes into play for interconnectivity.
It can be compared to the PCIe interconnect (discussed above), as both have a similar per-lane throughput. To keep scaling interconnect speed, advanced technologies in this domain are being used. Similarly, scaling SerDes also has its own challenges.
Intel beat Xilinx to market with 58G FPGAs, is starting to ship 116G for Agilex, and in August 2020 Intel was the first company to announce 224G PAM-4 (two bits per signal) transceiver IP running in the lab (seemingly on Intel 4).
Summary: Intel's Unparalleled FPGA leadership
Intel was one year behind Xilinx with the introduction of its Stratix 10 FPGA in 2017, but Versal and Agilex started sampling at around the same time in mid-2019. Agilex has also demonstrated leadership performance and efficiency. Note that it often takes 3-4 years for FPGA shipments to reach peak volume, given their longer customer design cycles. Looking forward, Intel is working on what might be a revolutionary FPGA, given the "1-2 orders of magnitude" improvement Intel cited.
Intel's FPGAs are notable because they have also been the launch vehicle for its latest packaging and chiplet technologies, resulting in an extensive chiplet library. Most notably, Intel's continuous transceiver leadership (58G-116G-224G) strengthens this view. Lastly, FPGAs also play a key part in Intel's AI strategy, and to support this, Intel's oneAPI software.
Altogether, Intel is deploying several of its most advanced technologies in FPGAs to achieve leadership. It remains to be seen if this will translate into corresponding market share gains.
While the go-to-market strategy of both companies is quite a bit different (for Intel: chiplets; for Xilinx: ACAPs), the goal of broadening the market for FPGAs, by making them more accessible is similar for both. This is achieved through higher-level tools such as oneAPI and Vitis (instead of the traditional low-level programming tools for FPGAs).
Overall, the conclusion from the comparison and analysis in this article is quite clear. Of course, investors will be eager to find out if this will result in any changes in market share and financials. At least based on the technology, especially if Intel moves forward with its paradigm-shift 3D FPGAs, then Xilinx might be in deep trouble.
So far this has not happened yet, with no truly remarkable market share shifts in the last few years. If anything, Intel actually posted some declines, as it reported that customers were transitioning from Intel FPGAs to Intel ASICs in the 5G segment.
So despite rather soft growth in FPGAs overall, after half a decade or so since the Altera acquisition, the most promising market for FPGAs arguably remains the data center, where they can function as IPU/DPU/SmartNIC or as an accelerator for AI or other workloads (since use-cases have already been demonstrated of FPGAs vastly outperforming Nvidia GPUs). It is unlikely FPGAs will ever become as mainstream as GPUs, but if these newer programming paradigms achieve at least some success (for example through oneAPI), then that may tremendously increase the addressable market, for both Intel and Xilinx.
This article was written by
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