## UPDATE 7/27/19

*Mike Bruzzone has provided more channel data - see first comment below. Sadly, the proportions are too volatile to use as the basis of volume predictions for unreleased SKUs.*

*I think the thesis that AMD is producing Zen2 chiplets in "hot" and "cold" batches still holds, but it's too early to draw any conclusions from relative proportions of SKUs.*

## FEOL Corners & Shooting Hot/Cold

Some days ago on Reddit, user nl3gt made some interesting posts in a thread in the r/AMD_Stock sub-Reddit..

nl3gt speculates that EPYC chiplets are fabbed in separate runs from Ryzen/TR chiplets. He points out that while using the same mask, between production runs the fab can tweak the doping parameters of the FinFETs to favor either high-frequency, leaky dies ("shooting the dies hot") or slower, less leaky dies ("shot cold").

[There's some background on the concept in this Wikipedia entry on FEOL Corners. Fabs routinely run batches at the doping extremes, or "corners" for each new mask stepping, to ensure that the design is electrically robust.]

## A Fabbing Thought-Experiment

To see why they might do this, let's do some imaginary fabbing (with made up numbers and simplified Math).

Imagine that AMD were to produce EPYZ & Ryzen chplets in a single batch, with mean TDP of, say, 15W, and mean boost clock frequency of, say, 4GHz.

Suppose then that only chiplets with TDP less than 15W were eligible for use in EPYC CPUs. Suppose the Normal Distribution curve above is a plot of TDP for all the chiplets produced in the batch. Obviously, 50% of working chiplets would have TDPs at or below the mean of 15W and would be candidates for use in EPYC.

Now imagine the plot shows the distribution of chiplet maximum boost frequency, and that 4GHz is the cut-off for Ryzen chiplets [these are made up numbers remember]. Again, 50% of working chiplets would be Ryzen candidates.

**Shooting Cold**

Now suppose that TSMC "juice" the parameters of the doping phase of the production run to favor slower-switching, less leaky FETs ("shooting the dies cold"). [To do this, I think, they increase the thickness of the diffusion layer by tinkering with doping solution concentration, treatment time, and temperature.]

Suppose this shifts the whole TDP distribution one standard deviation to the left. Using the same 15W TDP cut-off, we now find that 84% (everything to the left of the "60" label in the diagram above) of the chiplets will be EPYC candidates (while the number of more power-hungry Ryzen candidates is reduced).

**Shooting Hot**

In another run, TSMC might "shoot the dies hot", altering the doping solution concentration/temperature/etc. to skew the frequency distribution one standard deviation to the right. Here the run would produce 84% of chiplets with a boost frequency at or above our [made up] 4GHz hurdle.

We've used cut-offs at the mean of the "stock" distributions, and performance changes of one standard deviation to keep the Math simple. In real life the exercise is no doubt a frighteningly complicated multi-dimensional non-linear optimization problem. But, I hope this thought experiment has illustrated the potential benefits of having separate "hot" and "cold" production runs.

## The Ryzen 3000 Product Stack

Now perhaps we can explain the difference between the 3700x and the 3800x. I think 3700x chiplets are down-binned dies produced in a "cold" run targeting EPYC chiplets, with the up-binned chiplets being reserved for EPYC use. Similarly, the 3800x dies are likely down-binned dies from a "hot" run, with the better binned 8-core chiplets being reserved for the up-coming 3950x.

Similarly, the 3600 would be down-binned 6-core chiplets from a "cold" (EPYC) run, and the 3600x would be down-binned 3900x "hot" dies.

At last we can make sense of the Ryzen 3000 product stack. Why have two pairs of SKUs that differ by a few percentage points in performance, but by 50% in *rated* TDP? The simplest explanation is that they're drawn from two different production pools and can't be mixed without labeling them with the lowest (worst) common denominator TDP and speed (and risking class-action lawsuits).

## Grade Mix & Baskets - *SEE UPDATE ABOVE*

So, running with this theory for a moment, we're tantalizingly close to getting some hard data on TSMC production variability and yields.

Intel and AMD have to sell CPUs in baskets, weighted to match production output. Otherwise, for example, if Microcenter were to order a boatload of 3900Xs and AMD cranked up "hot" shoot production, they'd risk having unsold inventory of 3600Xs, 3800Xs and potential 3950Xs on their hands.

We can get some data on the production mix from a comment by Mike Bruzzone in a Seeking Alpha thread.

Here's grade SKU mix on Channel Data right now that is not yield I'd have to perform another calculation to estimate 8C dice yield, but can be described production yield taking into account packaging on final test.

3900X =62.5%

3800X = 5.35%

3700X = 8.03%

3600X = 6.25%

3600 =17.85%

(Elsewhere he gives proportions 70/6/9/7/20, which is close enough to the above numbers.)

## Estimating 3950X Volume - *SEE UPDATE ABOVE*

Unfortunately, this doesn't directly give us an idea of potential 3950X volumes, for comparison to the 3800X, but we can compare the proportions for the 2x6-hot-core 3900X and the 1x6-hot-core 3600X:

2 * 62.5% vs. 1 * 6.25%, i.e. **20 to 1**.

Things get a bit murky here, as there are a variety of ways in which a chiplet can become 6-core - including deliberate fusing of working cores for market segmentation purposes. But, assuming for a moment that at launch AMD wouldn't hobble good chiplets, **the down-bin SKU chiplet pools can be estimated to be one twentieth of the size of the up-bin SKU chiplet pools**.

If this proportion holds for the 8-hot-core chiplets, we can estimate the size of the pool of 3950x candidate chiplets as 20 times the size of the 3800X pool, or 2x53.5% relative to Mike's numbers above. So there might be 86% (53.5%/62.5%) as many available 3950Xs as 3900Xs. [Assuming all up-binned 8-hot-core dies are used.]

Some open questions are whether TR3 chiplets will be drawn from this pool? Will better quality chiplets be relegated to the 3800X pool as the products mature?

## Estimating EPYC Volume - *SEE UPDATE ABOVE*

In similar fashion, we can use the proportion of 3700Xs in the channel to estimate the potential number of up-binned 8-cold-core chiplets available for EPYC production as 2*80.3%. Remember, we have to divide this number by 8 to get the maximum number of possible 64C/128T EPYC CPUs, giving a maximum capacity of just over 20% of the current Ryzen channel unit volume.

Unfortunately, this number probably grossly over-estimates the size of the EPYC chiplet candidate pool. The ratio of up-bin to down-bin "cold" chiplets is probably much lower than 20:1. Another way to put this is that the TDP hurdle for EPYC chiplets is probably further from the default mean (measured in standard deviations) than is the frequency hurdle for "hot" chiplets.

We can take the above as an extreme upper bound and watch for Mike's channel data in order to convert this proportion into a unit count.

Meanwhile, we can take any change in the channel's proportion of 3700Xs to 3800Xs as a sign of increasing (or decreasing) EPYC production.

**Conclusions & Next Steps**

I'm not an Electrical Engineer and I've never worked in the semiconductor industry, so dope the above with a solution of Sodium Chloride. But, I hope this analysis helps shed some light on the reasons for AMD's slightly screwy Ryzen 3000 product stack.

I'm also not a Marketer, but I hope this helps better qualified observers like Mike Bruzzone to estimate production yields and volumes when channel stabilizes.

The end goal is to be able to predict what AMD management *really* thinks EPYC demand will be in the second half, which we can now observe through volumes of down-binned cold-core SKUs like the 3700X and 3600.

**Disclosure:** I am/we are long AMD.