See original SA report and comment line;
Bruce24 and Stock Market Mike.
Bruce, thanks for the Coffee Lake dice sizes; 157 and 127 mm^2.
Addressing interest, "to truly know who has the less expensive chip (AMD or Intel) you would need a lot of info we are never going to know. Such as what foundries are charging AMD v what it costs Intel to produce its own wafers at yields include cost of different packaging solutions."
On economic methods I'll take a stab at Epyc production cost on this simple metric;
Full Line AP $18800 / 11 grades = $1709 list / 3 = $569.69 GF/AMD/OEM SUPPORT $569.69 split of list price / 2 = GF production cost $284.84. Divide by rule is relied to estimate from design production hard cost buried into price; / 5 / 4 / 3 / 2.
Reference; "The implication of being able to use the cost function to describe accurately the technology in that the specification of a well behaved cost function is equivalent to the specification of a well behaved production function. Cost function (McFadden 1978) is a significant statistic for technology since all relevant information about the technology can be gleaned from the cost function. Referrals to Shephard 1953, 1970, Uzawa 1962, McFadden 1978, Diewart 1971" and I will add Beer 1966. I'm fairly certain these are the texts or equivalent to texts Barrett learned and taught from at Stanford, relied at similar industrial science departments in period.
One key to comprehending Intel science is the history of studies including academic works, relied by Intel, to define and defend a monopoly system's structure.
Apphttps://www.google.com/search?ei=dRBAWoD4BMrZ0gLf07WoDw&q=robert+chambers+applied+production+analysis&oq=robert+chambers+applied+production+analysis&gs_l=psy-ab.3...2691.11079.0.114188.8.131.52.184.108.40.2069.3602.21j8j3.32.0....0...1c.1.64.psy-ab..8.33.3000...0j46j0i131k1j0i67k1j0i131i67k1j0i46k1j0i22i30k1j33i160k1j33i21k1j33i22i29i30k1.0.bjFM3fcA53glied Production Analysis
There are more methods detailed in above book then I use; See Applied Production Analysis a Dual Approach, Robert Chambers, University of Maryland, Cambridge Press, 1988; 978-0-521-31427-5
SA audience can read back in my comment line to February 2017 where the following and other cost estimates are detailed back into 2012.
There is earlier analysis for FTC;
Alternatively Zeppelin dice $60 each x 4 = $240 + $40 to $60 packaging and final test; $280 to $300 each fully produced.
As a Check;
Epyc 7251 / 2 = $237.50 = cost low
Epyc 7281 / 2 = $325 = cost range
Check assumes industrial management best practice design manufacturer or producer will not price at or below cost. This is not always true for Intel where historically below cost production is averaged against margin bearing production.
Assessment; AMD Epyc makes progressively better margin up bin and Intel SP looses margin or takes a cost charge down bin where OEM/IDM volume price is less than component product lines full run marginal cost. Intel might argue grade SKUs price below category full run marginal cost are not priced below cost on reclaimed cost of salvage. Intel has moved away from good dice disablement to bin lower price grades but the practice of reclaim is designed in and widely relied by component fabricators and producers. This is not always an effective production method.
I have Ryzen average design production cost at $40.90 or $0.19 per mm^2 of area. GoFlo hard fabrication cost range estimated at 25% to 50% less on divide by 2's rule although this is a yield range statement improving above AMD Zeppelin 8C 50% yield.
AMD overall gross per component aim appears $108-ish across Zeppelin categories. Is Threadripper plus Ryzen combined Average Weighed Price on open market broker inventory holding ‘grades yield data' / 3; GF/AMD/OEM split of total component revenue. / 2 and / 3 are both examples of square procurement deals within the design production supply chain.
GF Marginal Cost of Zeppelin dice production on Total Revenue Total Cost Model using Ivy Bridge Production Metric: % production volume in quarter;
Current 12.23.17 AWP applied to first unit of production = $329.69
Reaching 8% of full run = $82.30
Reaching 69% peak production = $32.92
Production crest down through run end = $34.52
Full Run AWP $40.90
Haswell Production metric on a steeper ramp yields lower cost. I have most of the Intel ramp metrics either from supply signal cipher or seen in broker market inventory ramp. Both are Intel industry signal transmission systems.
Zeppelin dice full run AMC $40.96 is GF design production with package then adds GF mark up minimally on the square deal $40.96 thereafter $82 up to $108 to AMD dependent production phase; risk, ramp, peak, crest, run down, run end.
My prior 'preliminary' Xeon SP cost estimate on Intel $1K Price *.61 (39% OEM discount) / 11x margin attempts to find average marginal cost. At 9x to 11x price greater than average marginal cost enters Intel monopoly price threshold. Xeon SP definitely reaches above economic into the monopoly price range. In comparison E5 2600 v4 is commercially priced. Intel price on new reservation system; Platinum, Gold, Silver, Bronze, is up.
XCC dice that are 20 to 28 Cores $421.04.
HCC dice that are 12 to 18 Cores $120.98
LCC dice that are 4 to 10 Cores $83.66 with marginal cost of 4 core $60.84.
On TR/TC Method that is different from above method XSP full run marginal cost of $250 is $90 more than E5 2600 v4. Ultimately I have to calculate this by XCC, HCC, LCC grades. I've done that below for E5 2600 v4.
On Total Revenue Total Cost Method Xeon SP Marginal Cost Curve
AWP at 12.23.17 unit 1 $2014.58
Reaching 8% of run $503.64
Reaching 68% peak $201.36
Entering run down $209.02
Full Run AWP $250 down to $170.
Where I had $188 on an earlier estimate.
I agree with Bruce24 that the precise component cost when engineers calculate by weight of process material in, price of materials by weight, mass, volume, cost of development time, effort, fabrication goodwill is precise and generally unavailable.
My response to Bruce24, SA seems to want in stock talks section and not in comment line, "to truly know" these (COST) estimates are sufficient for industrial management, sales, operating decisions on model methods include Intel metrics aiming for best in class that is close enough for competitive comparison. For AMD to be industrially competitive means the adoption of some Intel techniques. Over time TR/TC Model shows production category and component's cost trajectories.
Over time for this FTC studies aid include Intel production micro economics on federal and states attorney’s discovery enlistment begins May 1998. I am former Cyrix, ARM, NexGen, AMD employee, Intel and IDT consultant. Intel production run assessments begin Pentium P5 in 1993. I've completed 158 that is essentially all of them.
My economic work tends to be qualitative over quantitative intercepting for interpreting Intel signal transmission and decomposing or recomposing Intel system structures including presenting in plots and graphs on price, supply, volume, yield and mechanics as this method produces pictorial data easier for United States Congress, regulatory including FTC and USDOJ, attorneys and law enforcement too understand. Academic oversight board is in place since before 2008.
There's almost enough data on Xeon SP cores data; XCC 28 to 20, HCC 18 to 12, LCC 10 to 4 for estimating cost trajectory but not today.
I previously posted this exercise to determine from Intel and AMD 57,000 mm2 wafer design production cost.
E5 2600 v4 Quick Method #1;
Intel 57,000 mm^2 / 456 mm^2 E5 2600 v4 master die = 125 dice
Average marginal cost of production using Intel Total Revenue Total Cost Model that in this instance is the Ivy Bridge metric on production in units per quarter @ $1K Price $160 * 125 dice = $20,000
E5 2600 v4 Quick Method #2;
On OEM/IDM 30% price discount application;
Average marginal cost adjustment TR/TC Model @ $1K Price $160 * .7 OEM/IDM 30% Price Discount = $112 * 125 dice = $14,014.
Working from Intel price delivers the production cost. Simply divide by 2 for fabrication cost. There are more precise ‘simple’ methods. This is a general tutorial.
E5 2600 v4 Intel Dice Size Method #3 is the more precise method I will eventually apply to Xeon SP.
Specific Broadwell E5 2600 v4;
LCC; 4 to 11C = 246 mm^2
HCC; 12 to 15C = 306 mm^2
XCC; 16 to 24C = 456 mm^2
Grade Split on open market broker inventory holding where that data becomes more precise over time;
4C = 0.09% (begin 246 mm^2)
6C = 0.11%
8C = 0.20%
10C = .14%
12C = .07% (begin 306 mm^2)
14C = .18%
16C = .04% (begin 456 mm^2)
18C = .09%
20C = .04%
22/24C = .04%
TR/TC Model Average Marginal Cost; Volume $1K Price * .7 that is OEM/IDM 30% price discount.
Note long run assessment reveals Intel high volume discount over 23 years approximately 50%.
Broker inventory and Intel 2016 financial suggest v4 discount to Cloud is up to 86%.
There are five reasons for deep cloud discount; architecture end of life, cloud procurement accommodating two Intel processor regimes, Haswell and Broadwell, in half the time, production volume required to yield v4 top bin, dumping the less than 12 core surplus as a competitor blockade, discount establishes E5 2600 v4 price floor offers sales time to the channel. At any higher discount channel would have been severely financial impacted and is across many Intel product category grades. The tailing, dregs and sludge of Intel production for this enterprise operation that historically competes on supply, not on demand, that is just changing now.
E5 2600 v4 Marginal Cost over Full Run;
4C = $55
6C = $71
8C = $71
10C = $71
12C = $107
16C = $161
18C = $224
20C = $281
22C = $357
24C = more $
On grade split E5 2600 v4 core grades per wafer;
04C = 11.25 dice
06C = 13.82 dice
08C = 25.30 dice
10C = 17.77 dice
12C = 09.16 dice
14C = 22.58 dice
16C = 04.69 dice
18C = 11.37 dice
20C = 04.41 dice (not many)
22C = 04.78 dice (not many)
Total = 125 dice/wafer
Normalized Dice Size on Grade Split 304 mm^2
At normalized dice size 57,000 / 304 = up to 187 components per wafer
Good Dice Area on Grade Split 37,988 mm^2 of total area.
66% Total Area Yield
Loss of 62 potential components over total wafer area.
Cost of Good Dice Area = $15,272.02
Cost of Bad Dice Area = $7,643
Total Cost per Wafer = $22,915 / 187 = $122.54 per component area shows E5 2600 v4 improvement over Haswell E5 2600 v3.
This is a different method from TR/TC delivering lower full run cost by $37.46 that is thought around Intel variable cost for v4 run on yet another method but still takes into account 86% cloud procurement discount.
E5 2600 Full Run Average Marginal Cost on Total Revenue Total Cost Method;
Ivy Bridge v2 = AMC $138
Haswell v3 = AMC $129
Broadwell v4 = AMC $160 down to $123.
Xeon SP preliminary = AMC $250 down to $175 (*.7)
NOW AMD Zeppelin 8C Optimized Mask Set on 213 mm^2.
57,000 / 213 = 267 potential components per wafer.
Best 8C average marginal design production cost 267 * $41 = $10,947 x 2 GF Margin = $21,894 out the door to AMD.
$21,894 is price difference between foundry and AMD the design producer, and Intel the design manufacturer. There are ways for AMD to negotiate a foundry margin over time anticipating foundry marginal cost improvements over full run.
Zeppelin Grade Split 12.23.17;
8C = 58%
6C = 21%
4C = 21%
On grade split Zeppelin core grades per wafer;
8C = 154 dice
6C = 56 dice
4C = 56 dice
There is no production dice size difference but I'll do the calculation.
Normalized dice size = 159.75 mm^2 that is Ryzen 6C median.
57,000 / 159.75 = 356 potential components.
Verse 267 good 8C suggest at least a 25% area loss reclaiming Ryzen 6/4C.
I'll do the wafer cost this way; 154 8C @ peak production $59.79 each + 112 6/4C at $34.51 run down cost of reclaim plus the area waste at $3,071.74 = $16,144.52 design production plus GF mark up 33% = $21,472 out the door to AMD that is a check against the $21,894 estimate above.
One answer to Bruce24 original question is when you add in GF margin, AMD design production cost is similar to Intel. Taking into account Intel slightly poorer yield ~ 9% or maybe slightly more, AMD Epyc dis-aggregated dice on interconnect in multi die package is an advantage verse Intel XSP up bin and less of an advantage v Intel XSP down bin.
Mike Bruzzone, Camp Marketing
Disclosure: I/we have no positions in any stocks mentioned, and no plans to initiate any positions within the next 72 hours.