Please Note: Blog posts are not selected, edited or screened by Seeking Alpha editors.

A Pillar Of Sparks: Interview With The RISC-V Foundation

Less than two months ago I published an article, claiming that the RISC-V architecture will take a more dominant position in the industry over time.

Since then there have been one major development - China Alibaba announced that it has developed the most advanced RISC-V chip yet.

I've also found out that the EU is developing a European processor initiative and India has developed its first chip ever using RISC-V. Two under discussed, possibly pivotal developments.

All of these events have picked my interest, and I’ve contacted the foundation and they have graciously agreed to answer a few questions to be published here on Seeking Alpha.

The questions for this interview were written by Oren Bokobza and answered by Ted Marena, chairman of the RISC-V Foundation Marketing Committee.

1.What are the advantages of having a reduced instruction set architecture (ISA) CPU? Are there any performance advantages? Lower heat output? Lower power consumption? The cost advantage is obvious, but what are the technological advantages?

RISC-V offers several advantages including its openness, simplicity, clean-slate design, modularity, extensibility and scalability. With the small fixed base ISA, engineers can choose to use modular fixed standard extensions or application-specific extensions to tailor solutions to their specific workloads. This enables a simpler design implementation which occupies a smaller silicon area. Designs can be optimized for higher performance, lower power, more robust security, etc.

2. What are the security advantages of lower instructions count?

Is it fair to assume that less CPU complexity == less vulnerabilities?

Because RISC-V has fewer instructions than many other architectures, the overall design is less complex. This on its own makes security easier to implement, but it is not the primary factor. RISC-V affords developers a clean sheet architecture to implement security from the ground up. There are two commercial examples which demonstrate this. Dover Microsystems has created CoreGuard, which is a hardware/software solution that sits between the processor and memory. It ensures the instructions which are being executed are appropriate. Hex Five has a solution called MultiZone Security. It provides hardware-enforced software-defined separation for an unlimited number of security domains, with full control over data, code and peripherals. Contrary to traditional solutions, Hex Five MultiZone requires no additional cores, specialized hardware or changes to existing software. Both of these solutions use very little resources and have negligible performance compromises.

3. Where can I see RISC-V cores in the industry?

Cores are implemented in a variety of solutions and devices from companies including Amazfit, Andes, Codasip, GreenWaves Technologies,Kendryte, Microchip Technology and SiFive.

Additionally, numerous RISC-V RTL cores can be searched at RISC-V Cores - RISC-V Foundation.

4. Can you please explain to us, as simply as you can, the generational leap between each RISC generation? (RISC I, II.. V) , Is there a paper we can read on the process and the outcome?

The first RISC I architecture was the result of analysis that only 30 percent of a CPU’s instructions were being used to run Unix. Hence a project was undertaken to create a processor with fewer instructions. The RISC II work was an efficiency improvement on RISC I. The design was streamlined and the implementation ran much faster. The third generation updated the design so it could run C code. The fourth generation modified the design to enable a 32 bit workstation to be built. The leap to RISC-V, the fifth generation of RISC, was a recognition that an open ISA (Instruction Set Architecture) that was scalable from 32, 64 and 128bit could be beneficial for a wide range of applications. When the ISA was frozen in 2014, commercial companies began to evaluate and adopt it. The RISC-V Foundation was then formed in 2015 to foster its growth.

This is a detailed resource on the RISC history at Berkeley for the first four iterations which you can read at: Berkeley RISC.

5. Since a Turing-complete machine could be accomplished by using just 1 instruction, why don’t you just “lock it down” and call it a day?

Modern processing requires additional instructions to accomplish a variety of tasks. The base instruction set of RISC-V is less than 50 total instructions.

6. What is the current status of x86 and ARM emulation on RISC-V processors?

Although some applications emulate other architectures, most developers today are writing software under a popular OS. If your software runs on an OS, then you are free to choose the best architecture for your development. Today RISC-V is supported by numerous Linux distributions and RTOS’s such as FreeRTOS, Zephyr, ThreadX, etc.

Disclosure: I/we have no positions in any stocks mentioned, and no plans to initiate any positions within the next 72 hours.

Additional disclosure: I wrote this article myself, and it expresses my own opinions. I am not receiving compensation for it.
I have no business relationship with any company whose stock is mentioned in this article.