Synopsys, a prominent software, IP, and services provider for use in the acceleration of innovation in chips and electronic systems, announced today Synopsys' IC Validator physical verification product has been qualified by United Microelectronics Corporation for 28-nm physical signoff, with immediate availability of design rule checking (NYSE:DRC) and layout-vs.-schematic (NYSE:LVS) runsets to UMC customers. IC Validator is an excellent compliment to IC Compiler™ for in-design physical verification. This capability allows for place-and-route engineers to decrease time to tapeout through the elimination of surprises and manual fixes in the later stages of the process. IC Validator is active at process nodes within the range from 65nm to 20nm. UMC's qualification of IC Validator provides design teams with the distinctive benefits of in-design physical verification when working at UMC's 28-nm process node.
"UMC is committed to making available to its customers solutions that ensure silicon success while optimizing design turnaround time. As such, optimal runset creation and efficient maintenance are of paramount importance," said SC Chien, vice president of Customer Engineering& IP Development Design Support at UMC. "Runset creation with IC Validator was completed in record time for our 28-nanometer process node. In addition, our IC Compiler customers can now take advantage of the productivity benefits of In-Design physical verification for faster design closure."
The number and complexity of DRCs required to achieve manufacturing compliance is growing at an exponential rate as geometries of features continue to shrink. IC Validator alleviates this strain by making runset generation and maintenance effortless for users by delivering a hybrid engine for processing checks using both polygon and edge data. Using hybrid processing allows for more efficient dependency resolution and increased intelligence of multi-core distribution, delivering quicker runtimes. In addition, IC Validator allows for near-linear performance scalability that optimizes utilization of mainstream components, through the application of smooth, memory-aware load scheduling and balancing technologies.
Traditional physical verification done after design closure is no longer adequate for complex designs, causing late-stage surprises and leading to an increasing number of time-consuming and error-prone design iterations. In-Design physical verification, based on intelligent integration between IC Validator and IC Compiler, makes it possible for place-and-route engineers to perform independent signoff-quality analysis earlier, before the design is finalized and while correction can be automated. In-Design technology enables new high-productivity functionality, such as automatic DRC repair, timing-aware metal fill, and rapid ECO validation, all within the place-and-route environment. In-Design physical verification eliminates entire iterations with downstream analysis tools and maintains convergent design evolution to physical signoff.
"As manufacturing complexity places increased pressure on our customers to deliver within schedule, it is important that we continue to collaborate closely with leading foundries like UMC," said Antun Domic, senior vice president and general manager of Synopsys' Implementation Group. "This qualification brings the proven benefits of IC Validator and In-Design physical verification to UMC's customers working at advanced nodes."
For further information, please visit www.synopsys.com
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